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Motorola MPC8260 User Manual

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MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV.  Communications Processor Module
 
Figure 29-55. Interrupt Queue Structure
29.11.2  Interrupt Queue Entry
Each one-word interrupt queue entry provides detailed interrupt information to the host.
Figure 29-56 shows an entry.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0x00
V
Ñ
W
Ñ
TBNR RXF BSY TXB RXB
Offset + 0x02
Channel Code (CC)
Figure 29-56. Interrupt Queue Entry 
V = 0
W = 0
Invalid
V = 0
W = 0
Invalid
V = 0
W = 0
Invalid
V = 1
W = 0
Interrupt Entry
V = 1
W = 0
Interrupt Entry
V = 1
W = 0
Interrupt Entry
V = 0
W = 0
Invalid
V = 0
W = 0
Invalid
V = 0
W = 1
Invalid
INTQ_BASE
Software (Core) Pointer
INTQ_PTR
Word