Motorola MPC8260 User Manual
29-81
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
29.11.3 Interrupt Queue Parameter Tables
The interrupt queue parameters are held in parameter tables in the dual-port RAM; see
Table 29-43. INTT_BASE in the parameter RAM points to the base address of these tables.
Each of the four interrupt queues has its own parameter table with a starting address given
by INTT_BASE+ RCT/TCT[INTQ]
Table 29-43. INTT_BASE in the parameter RAM points to the base address of these tables.
Each of the four interrupt queues has its own parameter table with a starting address given
by INTT_BASE+ RCT/TCT[INTQ]
´ 16.
Table 29-42. Interrupt Queue Entry Field Description
Offset Bits
Name
Description
0x00
0
V
Valid interrupt entry
0 This interrupt queue entry is free and can be use by the CP.
1 This interrupt queue entry is valid. The host should read this interrupt and clear this bit.
0 This interrupt queue entry is free and can be use by the CP.
1 This interrupt queue entry is valid. The host should read this interrupt and clear this bit.
1
Ñ
Reserved, should be cleared.
2
W
Wrap bit. When set, this is the last interrupt circular table entry. During initialization, the
host must clear all W bits in the table except the last one, which must be set.
host must clear all W bits in the table except the last one, which must be set.
3Ð10
Ñ
Reserved, should be cleared.
11
TBNR
Tx buffer-not-ready. Set when a transmit buffer-not-ready interrupt is issued. This interrupt
is issued when the CP tries to open a TxBD that is not ready (R = 0). This interrupt is sent
only if TCT[BNM] = 1. This interrupt has an associated channel code.
Note that for AAL5, this interrupt is sent only if frame transmission is started. In this case,
an abort frame transmission is sent (last cell with length=0), the channel is taken out of the
APC, and the TCT[VCON] ßag is cleared.
is issued when the CP tries to open a TxBD that is not ready (R = 0). This interrupt is sent
only if TCT[BNM] = 1. This interrupt has an associated channel code.
Note that for AAL5, this interrupt is sent only if frame transmission is started. In this case,
an abort frame transmission is sent (last cell with length=0), the channel is taken out of the
APC, and the TCT[VCON] ßag is cleared.
12
RXF
Rx frame. RXF is set when an Rx frame interrupt is issued. This interrupt is issued at the
end of AAL5 PDU reception. This interrupt is issued only if RCT[RXFM] = 1. This interrupt
has an associated channel code.
end of AAL5 PDU reception. This interrupt is issued only if RCT[RXFM] = 1. This interrupt
has an associated channel code.
13
BSY
Busy condition. The BD table or the free buffer pool associated with this channel is busy.
Cells were discarded due to this condition. This interrupt has an associated channel code.
Cells were discarded due to this condition. This interrupt has an associated channel code.
14
TXB
Tx buffer. TXB is set when a transmit buffer interrupt is issued. This interrupt is enabled
when both TxBD[I] and TCT[IMK] = 1. This interrupt has an associated channel code.
when both TxBD[I] and TCT[IMK] = 1. This interrupt has an associated channel code.
15
RXB
Rx buffer. RXB is set when an Rx buffer interrupt is issued. This interrupt is enabled when
both RxBD[I] and RCT[RXBM] = 1. This interrupt has an associated channel code.
both RxBD[I] and RCT[RXBM] = 1. This interrupt has an associated channel code.
0x02
Ñ
CC
Channel code speciÞes the channel associated with this interrupt.
Table 29-43. Interrupt Queue Parameter Table
Offset
1
Name
Width
Description
0x00
INTQ_BASE
Word
Base address of the interrupt queue. User-deÞned.
0x04
INTQ_PTR
Word
Pointer to interrupt queue entry. Initialize to INTQ_BASE.
0x08
INT_CNT
Half Word Interrupt counter. Initialize with INT_ICNT. The CP decrements INT_CNT for
each interrupt. When INT_CNT reaches zero, the queueÕs global interrupt ßag
FCCE[GINTx] is set.
FCCE[GINTx] is set.
0x0A
INT_ICNT
Half Word Interrupt initial count. User-deÞned global interrupt thresholdÑthe number of
interrupts required before the CP issues a global interrupt (FCCE[GINTx]).