Motorola DSP56012 User Manual
Parallel Host Interface
Host Interface (HI)
MOTOROLA
DSP56012 User’s Manual
4-33
Receive Low (RXL). These three registers receive data from the high byte, middle
byte, and low byte, respectively, of the HOTX register and are selected by three
external host address inputs (HOA[2:0]) during a host processor read operation or by
an on-chip address counter in DMA operations. The receive byte registers (at least
RXL) contain valid data when the Receive Data Register Full (RXDF) bit is set. The
host processor can program the RREQ bit to assert the external HOREQ pin when
RXDF is set. This informs the host processor or DMA controller that the receive byte
registers are full. These registers can be read in any order to transfer 8-, 16-, or 24-bit
data. However, reading RXL clears the receive data full RXDF bit. Because reading
RXL clears the RXDF status bit, it is normally the last register read during a 16- or
24-bit data transfer.
byte, and low byte, respectively, of the HOTX register and are selected by three
external host address inputs (HOA[2:0]) during a host processor read operation or by
an on-chip address counter in DMA operations. The receive byte registers (at least
RXL) contain valid data when the Receive Data Register Full (RXDF) bit is set. The
host processor can program the RREQ bit to assert the external HOREQ pin when
RXDF is set. This informs the host processor or DMA controller that the receive byte
registers are full. These registers can be read in any order to transfer 8-, 16-, or 24-bit
data. However, reading RXL clears the receive data full RXDF bit. Because reading
RXL clears the RXDF status bit, it is normally the last register read during a 16- or
24-bit data transfer.
Note:
Reset does not affect RXH, RXM, or RXL.
4.4.5.9
Transmit Byte Registers (TXH, TXM, TXL)
The transmit byte registers are viewed as three 8-bit write-only registers by the host
processor. These registers are called Transmit High (TXH), Transmit Middle (TXM),
and Transmit Low (TXL). These three registers send data to the high byte, middle
byte and low byte, respectively, of the HORX register and are selected by three
external host address inputs (HOA[2:0]) during a host processor write operation.
Data can be written into the transmit byte registers when the Transmit Data Register
Empty (TXDE) bit is set. The host processor can program the TREQ bit to assert the
external HOREQ pin when TXDE is set. This informs the host processor or DMA
controller that the transmit byte registers are empty. These registers can be written in
any order to transfer 8-, 16-, or 24-bit data. However, writing TXL clears the TXDE
bit. Because writing the TXL register clears the TXDE status bit, TXL is normally the
last register written during a 16- or 24-bit data transfer. The transmit byte registers
are transferred as 24-bit data to the HORX register when both TXDE and the HRDF
bit are cleared. This transfer operation sets TXDE and HRDF.
processor. These registers are called Transmit High (TXH), Transmit Middle (TXM),
and Transmit Low (TXL). These three registers send data to the high byte, middle
byte and low byte, respectively, of the HORX register and are selected by three
external host address inputs (HOA[2:0]) during a host processor write operation.
Data can be written into the transmit byte registers when the Transmit Data Register
Empty (TXDE) bit is set. The host processor can program the TREQ bit to assert the
external HOREQ pin when TXDE is set. This informs the host processor or DMA
controller that the transmit byte registers are empty. These registers can be written in
any order to transfer 8-, 16-, or 24-bit data. However, writing TXL clears the TXDE
bit. Because writing the TXL register clears the TXDE status bit, TXL is normally the
last register written during a 16- or 24-bit data transfer. The transmit byte registers
are transferred as 24-bit data to the HORX register when both TXDE and the HRDF
bit are cleared. This transfer operation sets TXDE and HRDF.
Note:
Reset does not affect TXH, TXM, or TXL.
4.4.5.10
Registers After Reset
seen by the host processor. The hardware reset is caused by asserting the RESET pin;
the software reset is caused by executing the RESET instruction; the individual reset
is caused by clearing the PBC register bit 0; and the stop reset is caused by executing
the STOP instruction.
the software reset is caused by executing the RESET instruction; the individual reset
is caused by clearing the PBC register bit 0; and the stop reset is caused by executing
the STOP instruction.