Motorola DSP56012 User Manual
Parallel Host Interface
Host Interface (HI)
MOTOROLA
DSP56012 User’s Manual
4-35
4.4.6
HI Signals
The fifteen HI signals are described here for convenience. Additional information,
including timing, is provided in the
including timing, is provided in the
DSP56012 Technical Data
sheet (DSP56012/D).
4.4.6.1
HI Data Bus (H0–H7)
This bidirectional data bus transfers data between the host processor and the
DSP56012. It acts as an input unless HEN is asserted and HR/W is high, making
H[7:0] become outputs and allowing the host processor to read DSP56012 data. It is
high impedance when HEN is deasserted. H[7:0] can be programmed as GPIO pins
(PB[7:0]) when the HI is not being used. These pins are configured as GPIO input
pins during hardware reset.
DSP56012. It acts as an input unless HEN is asserted and HR/W is high, making
H[7:0] become outputs and allowing the host processor to read DSP56012 data. It is
high impedance when HEN is deasserted. H[7:0] can be programmed as GPIO pins
(PB[7:0]) when the HI is not being used. These pins are configured as GPIO input
pins during hardware reset.
4.4.6.2
HI Address (HOA2–HOA0)
These inputs provide the address selection for each HI register. HOA[2:0] can be
programmed as GPIO pins (PB[10:8]) when the HI is not being used. These signals
are configured as GPIO inputs during hardware reset.
programmed as GPIO pins (PB[10:8]) when the HI is not being used. These signals
are configured as GPIO inputs during hardware reset.
4.4.6.3
HI Read/Write (HR/W)
The HI Read/Write (HR/W) signal selects the direction of data transfer for each host
processor access. If HR/W is high and HEN is asserted, H[7:0] are configured as
outputs and DSP data is transferred to the host processor. If HR/W is low and HEN
is asserted, H[7:0] are configured as inputs and host data is transferred to the DSP.
HR/W is stable when HEN is asserted. HR/W can be configured as a GPIO pin
(PB11) when the HI is not being used, and is configured as a GPIO input pin during
hardware reset.
processor access. If HR/W is high and HEN is asserted, H[7:0] are configured as
outputs and DSP data is transferred to the host processor. If HR/W is low and HEN
is asserted, H[7:0] are configured as inputs and host data is transferred to the DSP.
HR/W is stable when HEN is asserted. HR/W can be configured as a GPIO pin
(PB11) when the HI is not being used, and is configured as a GPIO input pin during
hardware reset.
4.4.6.4
HI Enable (HEN)
The HI Enable (HEN) input enables a data transfer on the host data bus. When HEN
is asserted and HR/W is high, H[7:0] become outputs and the host processor may
read DSP56012 data. When HEN is asserted and HR/W is low, H[7:0] become inputs.
When HEN is deasserted, host data is latched inside the DSP. Normally, a chip select
signal derived from host address decoding and an enable clock are used to generate
HEN. HEN can be configured as a GPIO pin (PB12) when the HI is not being used,
and is configured as a GPIO input pin during hardware reset.
is asserted and HR/W is high, H[7:0] become outputs and the host processor may
read DSP56012 data. When HEN is asserted and HR/W is low, H[7:0] become inputs.
When HEN is deasserted, host data is latched inside the DSP. Normally, a chip select
signal derived from host address decoding and an enable clock are used to generate
HEN. HEN can be configured as a GPIO pin (PB12) when the HI is not being used,
and is configured as a GPIO input pin during hardware reset.
4.4.6.5
Host Request (HOREQ)
The Host Request (HOREQ) open-drain output signal is used by the DSP56012 HI to
request service from the host processor, DMA controller, or simple external
controller. HOREQ can be connected to an interrupt request pin of a host processor, a
request service from the host processor, DMA controller, or simple external
controller. HOREQ can be connected to an interrupt request pin of a host processor, a