Motorola DSP56012 User Manual

in noisy environments; the bit-rate transfer is strictly limited. The wide-spike- 
tolerance filter mode is highly recommended for use in I

2

C bus systems as it fully 

conforms to the I

2

C bus specification and improves noise immunity.

HFM[1:0] are cleared during hardware reset and software reset. 

After changing the filter bits in the HCKR to a non-bypass mode (HFM[1:0] not equal 
to ‘00’), the programmer should wait at least ten times the tolerable spike width 
before enabling the SHI (setting the HEN bit in the HCSR). Similarly, after changing 
the I

2

C bit in the HCSR or the CPOL bit in the HCKR, while the filter mode bits are in 

a non-bypass mode (HFM[1:0] not equal to ‘00’), the programmer should wait at least 
ten times the tolerable spike width before enabling the SHI (setting HEN in the 
HCSR).

The HCSR is a 24-bit read/write register that controls the SHI operation and reflects 
its status. Each bit is described in one of the following paragraphs. When in the Stop 
state or during individual reset, the HCSR status bits are reset to their hardware-reset 
state, while the control bits are not affected.

The read/write control bit Host Enable (HEN) enables the overall operation of the 
SHI. When HEN is set, SHI operation is enabled. When HEN is cleared, the SHI is 
disabled (individual reset state, see below). The HCKR and the HCSR control bits are 
not affected when HEN is cleared. When operating in Master mode, HEN should be 
cleared only after the SHI is idle (HBUSY = 0). HEN is cleared during hardware reset 
and software reset.

While the SHI is in the individual reset state, SHI input pins are inhibited, output and 
bidirectional pins are disabled (high impedance), the HCSR status bits and the 
transmit/receive paths are reset to the same state produced by hardware reset or 
software reset. The individual reset state is entered following a one-instruction-cycle 
delay after clearing HEN. 

The read/write control bit HI

2

C selects whether the SHI operates in the I

2

C or SPI 

modes. When HI

2

C is cleared, the SHI operates in the SPI mode. When HI

2

C is set, 

the SHI operates in the I

2

C mode. HI

2

C affects the functionality of the SHI pins as 

described in 

. It is recommended that an SHI individual