Motorola DSP56012 User Manual

reset be generated (HEN cleared) before changing HI

2

C. HI

2

C is cleared during 

hardware reset and software reset.

The read/write control bits HM[1:0] select the size of the data words to be 
transferred, as shown in 

when the SHI is idle (HBUSY = 0). HM[1:0] are cleared during hardware reset and 
software reset.

These bits in HCSR are reserved and unused. They are read as 0s and should be 
written with 0s for future compatibility.

The read/write control bit HCSR FIFO-enable control (HFIFO) selects the size of the 
receive FIFO. When HFIFO is cleared, the FIFO has a single level. When HFIFO is set, 
the FIFO has 10 levels. It is recommended that an SHI individual reset be generated 
(HEN cleared) before changing HFIFO. HFIFO is cleared during hardware reset and 
software reset.

The read/write control bit HCSR Master (HMST) determines the operating mode of 
the SHI. If HMST is set, the interface operates in the Master mode. If HMST is 
cleared, the interface operates in the Slave mode. The SHI supports a single-master 
configuration, in both I

2

C and SPI modes. When configured as an SPI Master, the SHI 

drives the SCK line and controls the direction of the data lines MOSI and MISO. The 
SS line must be held deasserted in the SPI Master mode; if the SS line is asserted 
when the SHI is in SPI Master mode, a bus error will be generated (the HCSR HBER 
bit will be set—see 

 

configured as an I

2

C Master, the SHI controls the I

2

C bus by generating start events, 

clock pulses, and stop events for transmission and reception of serial data. It is 

SHI Data Size  

0

0

8-bit data

0

1

16-bit data

1

0

24-bit data

1

1

Reserved