Motorola DSP56012 User Manual

DSPs, one operating as an I

2

C master device and the other as an I

2

C slave device, 

enables full hardware handshaking.

A receive session is initiated if the R/W direction bit of the transmitted slave device 
address byte is set. Following a receive initiation, data in SDA line is shifted into 
IOSR MSB first. Following each received byte, an acknowledge (ACK = 0) is sent at 
the ninth clock pulse via the SDA line if the HIDLE control bit is cleared. Data is 
acknowledged bytewise, as required by the I

2

C bus protocol, and is transferred to the 

HRX FIFO when the complete word (according to HM0–HM1) is filled into IOSR. It 
is the responsibility of the programmer to select the correct number of bytes in an I

2

C 

frame so that they fit in a complete number of words. For this purpose, the slave 
device address byte does not count as part of the data, and therefore, it is treated 
separately.

If the I

2

C slave transmitter is acknowledged, it should transmit the next data byte. In 

order to terminate the receive session, the programmer should set the HIDLE bit at 
the last required data word. As a result, the last byte of the next received data word is 
not acknowledged, the slave transmitter releases the SDA line, and the SHI generates 
the stop event and terminates the session.

In a receive session, only the receive path is enabled and the HTX-to-IOSR transfers 
are inhibited. If the HRNE status bit is set, the HRX FIFO contains valid data, which 
may be read by the DSP. When the HRX FIFO is full, the SHI suspends the serial 
clock just before acknowledge. In this case, the clock will be reactivated when the 
FIFO is read (the SHI gives an ACK = 0 and proceeds receiving) or when HIDLE is set 
(the SHI gives ACK = 1, generates the stop event, and ends the receive session).

A transmit session is initiated if the R/W direction bit of the transmitted slave device 
address byte is cleared. Following a transmit initiation, the IOSR is loaded from HTX 
(assuming HTX is not empty) and its contents are shifted out, MSB-first, on the SDA 
line. Following each transmitted byte, the SHI controller samples the SDA line at the 
ninth clock pulse, and inspects the ACK status. If the transmitted byte was 
acknowledged (ACK = 0), the SHI controller continues transmitting the next byte. 
However, if it was not acknowledged (ACK = 1), the HBER status bit is set to inform 
the DSP side that a bus error (or overrun, or any other exception in the slave device) 
has occurred. Consequently, the I

2

C master device generates a stop event and 

terminates the session. 

HTX contents are transferred to the IOSR when the complete word (according to 
HM0–HM1) has been shifted out. It is, therefore, the responsibility of the 
programmer to select the right number of bytes in an I

2

C frame so that they fit in a