Compaq EV67 User Manual

Initialization and Configuration

As BiST completes, the TestStat_H pin is held low for 16 GCLK cycles. Then,  if BiST 
succeeds, the pin remains low. Otherwise, it is asserted. After successfully completing 
BiST, the 21264/EV67 then performs the SROM load sequence (described in Chapter 
11). After the SROM load sequence is finished, the 21264/EV67 deasserts SromOE_L.

After the deassertion of SromOE_L, the reset state machine enters the 
WAIT_ClkFwdRst1 state,  where the 21264/EV67 waits for the system to deassert 
ClkFwdReset_H. The 21264/EV67 samples the deasserting edge of ClkFwdReset_H  
to take synchronous actions. It uses this synchronous event to reset the clock forward-
ing interface, start the outgoing clocks, and deassert internal reset. The chip then waits 
264 cycles before issuing commands. The reset state machine is then in RUN and the 
21264/EV67 begins fetching code at address 0x780.

Table 7–4 lists signals relevant to the power-up flow, provides a short description of 
each, and any relevant constraints.

ClkIn_x 

Differential clocks that are 
inputs to PLL or are 
bypassed onto GCLK 
directly

Clocks must be running before DCOK_H is 
asserted.

VDD supply to PLL

must lead VDD.

VDD supply to the 21264/
EV67 chip logic (except 
PLL)

—

Logic signal to the 21264/
EV67 that the VDD supply 
is good

—

RESET pin asserted by 
SYSTEM to the 21264/
EV67

Reset_L must be asserted prior to DCOK_H and 
must remain asserted for at least 100 ms after 
DCOK_H is asserted.  This allows for PLL settling 
time.  Deassertion of Reset_L causes the 21264/
EV67 to ramp divisors to their final value and begin 
BiST.

ClkFwdRst_H 
Deassertion #1

Signal asserted by SYS-
TEM to synchronously 
commence built-in self-test 
and SROM load

ClkFwdRst_H must be deasserted after PLL has 
achieved its lock in its final divisor value (about 20 

µ

s).  The deassertion causes built-in self-test to 

begin on an internal clock cycle that corresponds to 
one framing clock cycle after ClkFwdRst_H is 
deasserted.  ClkFwdRst_H can be asserted after 
one frame clock cycle. See Figure 7–1.

ClkFwdRst_H 
Deassertion #2

Signal asserted by SYS-
TEM to initialize and reset 
clock forwarding interfaces

ClkFwdRst_H must be deasserted when the Cbox 
has loaded configuration information.  This occurs 
as the first part of the serial ROM load, after BiST 
is run.  Once ClkFwdRst_H is deasserted, the 
interface is initialized and can receive probe 
requests from the 21264/EV67.