Cypress CY7C68053 Manual De Usuario

Document # 001-06120 Rev *F

Page 33 of 39

Various sequence diagrams and examples are presented in this section.

Figure 9-13 shows the timing relationship of the SLAVE FIFO

signals during a synchronous FIFO read using IFCLK as the

synchronizing clock. The diagram illustrates a single read

followed by a burst read.

• At  t = 0 the FIFO address is stable and the signal SLCS is 

asserted (SLCS may be tied low in some applications). 

Note t

SFA

 has a minimum of 25 ns. This means that when 

IFCLK is running at 48 MHz, the FIFO address set-up time 

is more than one IFCLK cycle.

• At  t = 1, SLOE is asserted. SLOE is an output enable only 

whose sole function is to drive the data bus. The data that 

is driven on the bus is the data that the internal FIFO pointer 

is currently pointing to. In this example it is the first data 

value in the FIFO. Note The data is pre-fetched and is driven 

on the bus when SLOE is asserted.

• At  t = 2, SLRD is asserted. SLRD must meet the set-up 

time of t

SRD

 (time from asserting the SLRD signal to the 

rising edge of the IFCLK) and maintain a minimum hold time 

of t

RDH

 (time from the IFCLK edge to the deassertion of the 

SLRD signal). If the SLCS signal is used, it must be asserted 

with SLRD, or before SLRD is asserted (for example, the 

SLCS and SLRD signals must both be asserted to start a 

valid read condition).

• The FIFO pointer is updated on the rising edge of the IFCLK 

while SLRD is asserted. This starts the propagation of data 

from the newly addressed location to the data bus. After a 

propagation delay of t

XFD

 (measured from the rising edge 

of IFCLK) the new data value is present. N is the first data 

value read from the FIFO. In order to have data on the FIFO 

data bus, SLOE MUST also be asserted.

The same sequence of events is shown for a burst read and is

marked with the time indicators of T = 0 through 5. Note For

the burst mode, the SLRD and SLOE are left asserted during

the entire duration of the read. In the burst read mode, when

SLOE is asserted, data indexed by the FIFO pointer is on the

data bus. During the first read cycle on the rising edge of the

clock, the FIFO pointer is updated and increments to point to

address N+1. For each subsequent rising edge of IFCLK while

the SLRD is asserted, the FIFO pointer is incremented and the

next data value is placed on the data bus.

t=0

t=1

t=2

t=3

t=4

T=0

T=1

T=2

T=3

T=4

N

N

N+1

N+2

N+3

N+4

Not Driven

Driven: N

SLOE

SLRD

N+1

N+2

N+3

Not Driven

SLRD

SLOE

IFCLK

IFCLK

IFCLK

IFCLK

IFCLK

N+4

N+4

IFCLK

IFCLK

IFCLK

IFCLK

SLRD

N+1

SLRD

N+1

N+1

SLOE

Not Driven

N+4

N+4

IFCLK

SLOE