Manual De UsuarioTabla de contenidos1.0 CY7C68053 Features12.0 Applications23.0 Functional Overview23.1 USB Signaling Speed23.2 8051 Microprocessor23.2.1 8051 Clock Frequency23.2.2 Special Function Registers23.3 I2C™ Bus33.4 Buses33.5 USB Boot Methods33.6 ReNumeration™33.7 Bus-powered Applications33.8 Interrupt System33.8.1 INT2 Interrupt Request and Enable Registers33.8.2 USB Interrupt Autovectors33.9 Reset and Wakeup53.9.1 Reset Pin53.9.2 Wakeup Pins53.9.3 Lowering Suspend Current53.10 Program/Data RAM63.10.1 Size63.10.2 Internal Code Memory63.11 Register Addresses63.12 Endpoint RAM63.12.1 Size63.12.2 Organization63.12.3 Set-up Data Buffer63.12.4 Endpoint Configurations (High-speed Mode)63.12.5 Default Full-Speed Alternate Settings73.12.6 Default High-Speed Alternate Settings83.13 External FIFO Interface83.13.1 Architecture83.13.2 Master/Slave Control Signals83.13.3 GPIF and FIFO Clock Rates83.14 GPIF83.14.1 Three Control OUT Signals93.14.2 Two Ready IN Signals93.14.3 Long Transfer Mode93.15 ECC Generation[6]93.15.1 ECC Implementation93.16 USB Uploads and Downloads93.17 Autopointer Access93.18 I2C Controller93.18.1 I2C Port Pins93.18.2 I2C Interface Boot Load Access103.18.3 I2C Interface General Purpose Access104.0 Pin Assignments104.1 CY7C68053 Pin Descriptions125.0 Register Summary166.0 Absolute Maximum Ratings237.0 Operating Conditions238.0 DC Characteristics249.0 AC Electrical Characteristics259.1 USB Transceiver259.2 GPIF Synchronous Signals259.3 Slave FIFO Synchronous Read269.4 Slave FIFO Asynchronous Read279.5 Slave FIFO Synchronous Write289.6 Slave FIFO Asynchronous Write299.7 Slave FIFO Synchronous Packet End Strobe299.8 Slave FIFO Asynchronous Packet End Strobe309.9 Slave FIFO Output Enable319.10 Slave FIFO Address to Flags/Data319.11 Slave FIFO Synchronous Address329.12 Slave FIFO Asynchronous Address329.13 Sequence Diagram339.13.1 Single and Burst Synchronous Read Example339.13.2 Single and Burst Synchronous Write349.13.3 Sequence Diagram of a Single and Burst Asynchronous Read359.13.4 Sequence Diagram of a Single and Burst Asynchronous Write3610.0 Ordering Information3711.0 Package Diagram3712.0 PCB Layout Recommendations38Tamaño: 1 MBPáginas: 39Language: EnglishManuales abiertas