Cypress CY7C68053 Manual De Usuario

Document # 001-06120 Rev *F

Page 35 of 39

Figure 9-16 illustrates the timing relationship of the SLAVE

FIFO signals during an asynchronous FIFO read. It shows a

single read followed by a burst read.

• At  t = 0, the FIFO address is stable and the SLCS signal is 

asserted.

• At  t = 1, SLOE is asserted. This results in the data bus being 

driven. The data that is driven on to the bus is previous data; 

it is data that was in the FIFO from a prior read cycle. 

• At  t = 2, SLRD is asserted. The SLRD must meet the min-

imum active pulse of t

RDpwl

 and minimum de-active pulse 

width of t

RDpwh

. If SLCS is used then, SLCS must be as-

serted with SLRD or before SLRD is asserted (for example, 

the SLCS and SLRD signals must both be asserted to start 

a valid read condition).

• The data that is driven, after asserting SLRD, is the updated 

data from the FIFO. This data is valid after a propagation 

delay of t

XFD

 from the activating edge of SLRD. In Figure 9-

16, data N is the first valid data read from the FIFO. For data 

to appear on the data bus during the read cycle (for example, 

SLRD is asserted), SLOE MUST be in an asserted state. 

SLRD and SLOE can also be tied together.

The same sequence of events is also shown for a burst read

marked with T = 0 through 5. Note In burst read mode, during

SLOE assertion, the data bus is in a driven state and outputs

the previous data. Once SLRD is asserted, the data from the

FIFO is driven on the data bus (SLOE must also be asserted)

and then the FIFO pointer is incremented.

t=0

T=0

T=1

T=7

T=2

T=3

T=4

T=5

T=6

t=1

t=2

t=3

t=4

N

N

SLOE

SLRD

N+3

FIFO DATA BUS Not Driven

Driven: X

N

 Not Driven

SLOE

N

N+2

N+3

SLRD

N

N+1

SLRD

N+1

SLRD

N+1

N+2

SLRD

N+2

SLRD

N+2

N+1

SLOE

Not Driven

SLOE

N

N+1

N+1