Cypress CY14B108N Manual De Usuario

Document #: 001-45523 Rev. *B

Page 5 of 24

STORE operation is completed, the CY14B108L/CY14B108N

remains disabled until the HSB pin returns HIGH. Leave the HSB

unconnected if it is not used.

During power up or after any low power condition

(V

CC

< V

SWITCH

), an internal RECALL request is latched. When

V

CC

 again exceeds the sense voltage of V

SWITCH

, a RECALL

cycle is automatically initiated and takes t

HRECALL

 to complete.

During this time, HSB is driven LOW by the HSB driver.

Transfer data from the SRAM to the nonvolatile memory with a

software address sequence. The CY14B108L/CY14B108N

Software STORE cycle is initiated by executing sequential CE

controlled read cycles from six specific address locations in

exact order. During the STORE cycle an erase of the previous

nonvolatile data is first performed, followed by a program of the

nonvolatile elements. After a STORE cycle is initiated, further

input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used

for STORE initiation, it is important that no other read or write

accesses intervene in the sequence, or the sequence is aborted

and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read

sequence must be performed.

1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle

The software sequence may be clocked with CE controlled reads

or OE controlled reads. After the sixth address in the sequence

is entered, the STORE cycle commences and the chip is

disabled. HSB is driven LOW.

 

It is important to use read cycles

and not write cycles in the sequence, although it is not necessary

that OE be LOW for a valid sequence. After the t

STORE

 cycle time

is fulfilled, the SRAM is activated again for the read and write

operation.

Transfer the data from the nonvolatile memory to the SRAM with

a software address sequence. A Software RECALL cycle is

initiated with a sequence of read operations in a manner similar

to the Software STORE initiation. To initiate the RECALL cycle,

the following sequence of CE controlled read operations must be

performed.

1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle

Internally, RECALL is a two-step procedure. First, the SRAM

data is cleared; then, the nonvolatile information is transferred

into the SRAM cells. After the t

RECALL

 cycle time, the SRAM is

again ready for read and write operations. The RECALL

operation does not alter the data in the nonvolatile elements.