SMSC LAN1198 Manual De Usuario
LAN9118 Family Programmer Reference Guide
SMSC AN 12.12
15
Revision 1.0 (12-14-09)
APPLICATION NOTE
5 Initialization
5.1 MAC Initialization
The ID_REV register is a good starting point from which to begin initialization, in that it provides a
known location in memory containing a known value; in the case of a LAN9118, revision B, the value
is 0x1180001. Typical usage is twofold. One is as a probe point, while the other use is as a
d i s c r i m i n a t o r o f t h e L A N 9 11 8 F a m i l y m e m b e r. T h e d e s i g n a t i o n o f t h e c h i p
(0x0118/0x0117/0x0116/0x0115) is found in the upper 16-bits of the register, while the step revision is
obtained from the lower 16-bits.
known location in memory containing a known value; in the case of a LAN9118, revision B, the value
is 0x1180001. Typical usage is twofold. One is as a probe point, while the other use is as a
d i s c r i m i n a t o r o f t h e L A N 9 11 8 F a m i l y m e m b e r. T h e d e s i g n a t i o n o f t h e c h i p
(0x0118/0x0117/0x0116/0x0115) is found in the upper 16-bits of the register, while the step revision is
obtained from the lower 16-bits.
The BYTE_TEST register is provided to confirm the byte ordering of the host-device interface. The
interface between the host and the device is designed correctly when the host can read this register
as having a value of 0x87654321.
interface between the host and the device is designed correctly when the host can read this register
as having a value of 0x87654321.
5.1.1 Software Reset of the MAC
Before performing a software reset operation to the MAC, the driver should ensure that the internal
PHY is running. This can be determined by examining the PMT_CTL:PM_MODE field for any power-
down state (non-zero). If this is found to be the case, a write to the BYTE_TEST register (a non-
destructive write to a read-only register), followed by polling the PMT_CTL:READY bit until clear, will
guarantee the PHY to be active and the initialization ready to continue.
PHY is running. This can be determined by examining the PMT_CTL:PM_MODE field for any power-
down state (non-zero). If this is found to be the case, a write to the BYTE_TEST register (a non-
destructive write to a read-only register), followed by polling the PMT_CTL:READY bit until clear, will
guarantee the PHY to be active and the initialization ready to continue.
When the driver is aware of the device, a software reset should be performed by writing a ‘1’ value to
the HW_CFG:HW_CFG_SRST bit. This bit is self clearing and can be polled to determine when to
continue. Having finished the reset, the driver may then set the transmit FIFO size to a default value
of 5 KB (HW_CFG:TX_FIF_SZ field, which is 5 KB after reset).
the HW_CFG:HW_CFG_SRST bit. This bit is self clearing and can be polled to determine when to
continue. Having finished the reset, the driver may then set the transmit FIFO size to a default value
of 5 KB (HW_CFG:TX_FIF_SZ field, which is 5 KB after reset).
5.1.2 FIFO Allocation and Flow-Control Configuration
Then set the Automatic Flow Control Configuration (AFC_CFG) register High Level to a value of 7
KB (110, or 0x006e) and the Low Level control to a value of 3.5 KB (55, or 0x37), which breaks the
FIFO up roughly in thirds. Also set the Backpressure duration to 50us for 100m operation (0x4), and
500 us for 10m operation.
KB (110, or 0x006e) and the Low Level control to a value of 3.5 KB (55, or 0x37), which breaks the
FIFO up roughly in thirds. Also set the Backpressure duration to 50us for 100m operation (0x4), and
500 us for 10m operation.
5.1.3 Setting the MAC Address
5.1.3.1 The Unicast Address Register
LAN9118 Family members offer one 48-bit perfect (exact) address, whose value is divided between
the MAC ADDRH and ADDRL registers. This address identities the controller to the LAN on which it
is attached.
the MAC ADDRH and ADDRL registers. This address identities the controller to the LAN on which it
is attached.
5.1.3.2 How a MAC Address is Stored
As an example, suppose the MAC address source address is supposed to be “1a:2b:3c:4d:5e:6f”,
where “1a” is the first octet sent on the wire. To do this, write the portion “6f5e” as the low 16-bits of
the ADDRH register value and write the address portion “4d3c2b1a” to the ADDRL register.
where “1a” is the first octet sent on the wire. To do this, write the portion “6f5e” as the low 16-bits of
the ADDRH register value and write the address portion “4d3c2b1a” to the ADDRL register.
5.1.3.3 Reloading the MAC Address from EEPROM
When a software reset operation is performed, it also starts the EEPROM reload cycle. To ensure that
the EEPROM has finished loading, poll the EEPROM Command register (E2P_CMD) busy bit until
clear. The loading should complete in under a millisecond. Upon completion, the
MAC_Address_Loaded bit in the command register can be examined for success. This step should
be completed before the driver sets up the General Purpose I/O configuration (GPIO_CFG), since
some I/O pins are shared between EEPROM and GPIO usage.
the EEPROM has finished loading, poll the EEPROM Command register (E2P_CMD) busy bit until
clear. The loading should complete in under a millisecond. Upon completion, the
MAC_Address_Loaded bit in the command register can be examined for success. This step should
be completed before the driver sets up the General Purpose I/O configuration (GPIO_CFG), since
some I/O pins are shared between EEPROM and GPIO usage.