SMSC LAN1198 Manual De Usuario
LAN9118 Family Programmer Reference Guide
Revision 1.0 (12-14-09)
16
SMSC AN 12.12
APPLICATION NOTE
Besides the MAC address, no other values are automatically loaded to the controller from EEPROM
in a reload cycle.
in a reload cycle.
5.1.3.4 Saving the MAC Address to EEPROM
A likely scenario during the manufacturing phase is to fix the MAC address of the host in the EEPROM
after assembly. There may also be valid reasons where the driver would allow a user to change the
MAC address after manufacture or startup. To reprogram the EEPROM under the control of the
controller, first ensure that the address in the MAC ADDRx register is correct.
after assembly. There may also be valid reasons where the driver would allow a user to change the
MAC address after manufacture or startup. To reprogram the EEPROM under the control of the
controller, first ensure that the address in the MAC ADDRx register is correct.
Then write the signature value of 0xa5 to the first location in EEPROM, followed by the MAC address
as shown in
as shown in
below:
:
5.2 Configuring Interrupts
All LAN9118 Family members provide an interrupt request signal (IRQ), which can easily be
programmed for a variety of hardware environments.
programmed for a variety of hardware environments.
5.2.1 Configuring the IRQ Pin
The polarity of the IRQ pin can be programmed to be active low or active high by setting the IRQ_POL
bit in the INT_CFG register (1=high, 0=low). This programmability enables the device to accommodate
a variety of processors with minimal external support circuitry.
bit in the INT_CFG register (1=high, 0=low). This programmability enables the device to accommodate
a variety of processors with minimal external support circuitry.
The buffer-type of the IRQ pin can also be programmed to be either Open-Drain or Push-Pull by setting
the IRQ_TYPE bit in the INT_CFG register (1 = Push-pull, 0 = Open Drain). If the Open-Drain setting
is chosen, the polarity defaults to active low, and the setting of the IRQ_POL bit is ignored.
the IRQ_TYPE bit in the INT_CFG register (1 = Push-pull, 0 = Open Drain). If the Open-Drain setting
is chosen, the polarity defaults to active low, and the setting of the IRQ_POL bit is ignored.
Once triggered, the IRQ output remains in an active state until acknowledged by the host.
5.2.2 Setting The Interrupt De-assertion Period
The interrupt de-assertion timer sets a minimum interval between assertions of the interrupt pin,
allowing the host to control the percentage of time it dedicates to servicing the device, even during
periods of heavy network traffic. The field controlling this timer (INT_DEAS) is located in the upper
8-bits field of the main interrupt configuration register (INT_CFG). This timer counts in 10us increments.
The correct value for this timer depends on the processor, operating system and application. The Linux
driver maintained on the SMSC website uses a de-assertion period of 220us (22d).
allowing the host to control the percentage of time it dedicates to servicing the device, even during
periods of heavy network traffic. The field controlling this timer (INT_DEAS) is located in the upper
8-bits field of the main interrupt configuration register (INT_CFG). This timer counts in 10us increments.
The correct value for this timer depends on the processor, operating system and application. The Linux
driver maintained on the SMSC website uses a de-assertion period of 220us (22d).
5.2.3 Enabling and Disabling Interrupts
Individual interrupts are controlled through the interrupt enable register (INT_EN) via read-modify-write
operations. First read this register. To enable specific interrupts, OR the contents with a bit-mask which
operations. First read this register. To enable specific interrupts, OR the contents with a bit-mask which
Table 5.1 EEPROM MAC Address Layout
ADDRESS
CONTENTS
0
0xa5
1
0x1a
2
0x2b
3
0x3c
4
0x4d
5
0x5e
6
0x6f