SMSC LAN1198 Manual De Usuario
LAN9118 Family Programmer Reference Guide
Revision 1.0 (12-14-09)
24
SMSC AN 12.12
APPLICATION NOTE
4. The PHY_CLK_SEL field must be set to 10b. This action will disable the MII clocks from the internal
and external PHYs to the controller’s internal logic.
5. The host must wait a period of time not less than 5 cycles of the slowest operating PHY clock
before executing the next step in this procedure. For example, if the internal PHY was operating
in 10Mbs mode, and the external PHY was operating at 100Mbs mode, the internal PHY’s TX_CLK
and RX_CLK period is the longest, and will determine the required wait time. In this case the
TX_CLK and RX_CLK period for the internal PHY is 400ns, therefore the host must wait 2us
(5*400ns) before proceeding. If the clocks of the device being deselected by the switch are not
running, they are not considered in this calculation.
in 10Mbs mode, and the external PHY was operating at 100Mbs mode, the internal PHY’s TX_CLK
and RX_CLK period is the longest, and will determine the required wait time. In this case the
TX_CLK and RX_CLK period for the internal PHY is 400ns, therefore the host must wait 2us
(5*400ns) before proceeding. If the clocks of the device being deselected by the switch are not
running, they are not considered in this calculation.
6. Set EXT_PHY_SEL to the desired MII port. This step switches the RXD[3:0], RX_DV, RX_ER,
TXD[3:0], TX_EN, CRS and COL signals to the desired port.
7. Set PHY_CLK_SEL to the desired port. This must be the same port that is selected by
EXT_PHY_SEL.
8. The host must wait a period of time of not less than 5 cycles of the slowest, newly enabled clock
before executing the next step in this procedure.
9. Enable the transmitter.
10. Enable the receiver.
11. The process is complete. The controller is ready to access the new PHY.
The above procedure must be repeated each time the MII port is switched. The procedure is identical
whether switching from internal PHY to external MII, or vice-versa.
whether switching from internal PHY to external MII, or vice-versa.
5.8 Examples of PHY MII Register Reads and Writes
A stated previously, it is better to access the PHY through a pair of routines that access the MAC
registers from the MAC_CSR_ registers, and a pair of routines that access the PHY registers from the
MII_ registers using the MAC register routines. The following examples are meant to only to illustrate
the concept of accessing the PHY registers.
registers from the MAC_CSR_ registers, and a pair of routines that access the PHY registers from the
MII_ registers using the MAC register routines. The following examples are meant to only to illustrate
the concept of accessing the PHY registers.
Example 1: Write the value 0x01e1 to the PHY Auto-Negotiation Advertisement Register
(register 4; advertise all capabilities when auto-negotiating)
(register 4; advertise all capabilities when auto-negotiating)
Step One:
Load the value (0x01e1) destined for PHY Auto-negotiation Advertisement register (4) into the
MAC_CSR_Data Register. Only the lower 16 bits will be written to the MII DATA register, and
eventually that will be written to the PHY itself.
MAC_CSR_Data Register. Only the lower 16 bits will be written to the MII DATA register, and
eventually that will be written to the PHY itself.
Step Two:
Write the command word into the MAC_CSR_CMD register. This causes the contents of the
MAC_CSR_Data register to be written (R/nW == 0) into the MII Data register (0x07).
MAC_CSR_Data register to be written (R/nW == 0) into the MII Data register (0x07).
MAC_CSR_DATA (TO BE LOADED INTO MII DATA REGISTER
Reserved
(31:16)
PHY Data
(15:0)
0x01E!
MAC_CSR_CMD
CSR Busy
R/nW
Reserved (29:8)
CSR Address (7:0)
1
0
0x07