SMSC LAN1198 Manual De Usuario

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LAN9118 Family Programmer Reference Guide
Revision 1.0 (12-14-09)
22
SMSC AN 12.12
APPLICATION NOTE
 
Basic Control Register (index 0) and completes when the Auto-negotiate Complete bit (5) is set in
the Basic Status Register (index 1).  Auto-negotiate Complete status should be available within 1.5
seconds.  Beyond this time, the driver can then probe for the reason of the failure, such as link down
or remote fault, and additionally schedule a thread to revisit the PHY initialization periodically until a
proper link has been established.
Once link has been established, the driver can set the MAC_CR:RDPX duplex mode to follow the
settings of the PHYs Basic Status Register  (10Base-T Full Duplex,  100Base-T Full Duplex).  If
auto-negotiation is enabled, then duplex mode can by found by the following sequence:
„
AutoNegotiationAdvertisement= ReadPhy(index:4)
„
AutoNegotiationLinkPartnerAbility= ReadPhy(index:5)
„
AutoNegotiationCompatableSpeeds= AutoNegotiationAdvertisement & 
AutoNegotiationLinkPartnerAbility
„
If (AutoNegotiationCompatableSpeeds & 100Base-T Full Duplex) <speed is 100 Mbits, full duplex>
„
If (AutoNegotiationCompatableSpeeds & 100Base-T) <speed is 100 Mbits, half duplex>
„
If (AutoNegotiationCompatableSpeeds & 10Base-T Full Duplex)<speed is 10 Mbits, full duplex>
„
If (AutoNegotiationCompatableSpeeds & 10Base-T)<speed is 10 Mbits, half duplex>
Driver writers can derive their own access routines for manipulating the PHY by examining the drivers
available from the SMSC website for the LAN9118 Family members. (
5.7   Switching Between Internal and External PHYs
Drivers for the LAN9117 and LAN9115, which support an external PHY, will need to poll the external
MII address space to detect those PHYs.  Valid addresses range from 2 to 31, while address 0 is
generally considered reserved.
The steps outlined in the flow diagram in 
, along with accompanying text, detail the required
procedure for switching the MII port, including the MII clocks. These steps must be followed in order
to guarantee clean switching of the MII ports.