SMSC LAN1198 Manual De Usuario
LAN9118 Family Programmer Reference Guide
Revision 1.0 (12-14-09)
6
SMSC AN 12.12
APPLICATION NOTE
3.1 Directly Addressable Registers
These registers are also referred to as “Slave Registers”.
Table 3.1 LAN9118 Family Directly Addressable Register Map
OFFSET
SYMBOL
REGISTER NAME
DEFAULT
50h
ID_REV
Chip IP and Rev
01180001h
54h
INT_CFG
Main Interrupt Configuration
00000000h
58h
INT_STS
Interrupt Status
00000000h
5Ch
INT_EN
Interrupt Enable Register
00000000h
60h
RESERVED
Reserved for future use
-
64h
BYTE_TEST
Read-only byte order testing register
87654321h
68h
FIFO_INT
FIFO Level Interrupts
48000000h
6Ch
RX_CFG
Receive Configuration
00000000h
70h
TX_CFG
Transmit Configuration
00000000h
74h
HW_CFG
Hardware Configuration
00000800h
78h
RX_DP_CTRL
RX Datapath Control
00000000h
7Ch
RX_FIFO_INF
Receive FIFO Information
00000000h
80h
TX_FIFO_INF
Transmit FIFO Information
00001200h
84h
PMT_CTRL
Power Management Control
00000000h
88h
GPIO_CFG
General Purpose IO Configuration
00000000h
8Ch
GPT_CFG
General Purpose Timer
0000FFFFh
90h
GPT_CNT
General Purpose Timer Count
0000FFFFh
94h
RESERVED
Reserved for future use
-
98h
WORD_SWAP
WORD_SWAP
00000000h
9Ch
FREE_RUN
Free Run Counter
-
A0h
RX_DROP
RX Dropped Frames Counter
00000000h
A4h
MAC_CSR_CMD
These two registers are used to
access the MAC CSRs.
00000000h
A8h
MAC_CSR_DATA
00000000h
ACh
AFC_CFG
Automatic Flow Control
00000000h
B0h
E2P_CMD
These two registers are used to
access the EEPROM
00000000h
B4h
E2P_DATA
00000000h
B8h - FCh
RESERVED
Reserved for future use
-