SMSC LAN1198 Manual De Usuario
LAN9118 Family Programmer Reference Guide
Revision 1.0 (12-14-09)
8
SMSC AN 12.12
APPLICATION NOTE
3.4 Restrictions on Read-Follow-Write CSR Accesses
There are timing restrictions on successive operations to some CSRs. These restrictions come into
play whenever a write operation to a control register is followed by a read operation from a related
register. These restrictions arise because of internal delays between write operations and their effects.
For example, when the TX Data FIFO is written, there is a delay of up to 135ns before the
TX_FIFO_INF register changes.
play whenever a write operation to a control register is followed by a read operation from a related
register. These restrictions arise because of internal delays between write operations and their effects.
For example, when the TX Data FIFO is written, there is a delay of up to 135ns before the
TX_FIFO_INF register changes.
In order to prevent the host from reading invalid status, minimum wait periods have been established
following write operations to each CSR. These periods are specified in
following write operations to each CSR. These periods are specified in
below. For each CSR,
the host is required to wait the specified period of time after a write before performing any read. These
wait periods are for read operations that immediately follow any write cycle. Note that the required wait
period is dependant upon the register being read after the write.
wait periods are for read operations that immediately follow any write cycle. Note that the required wait
period is dependant upon the register being read after the write.
Performing “dummy” reads of the BYTE_TEST register is a convenient way to guarantee that the
minimum write-to-read timing restriction is met.
minimum write-to-read timing restriction is met.
below also shows the number of dummy
reads that are required before reading the register indicated. The number of BYTE_TEST reads in this
table is based on the minimum timing for Tcyc (45ns). For microprocessors with slower busses, the
number of reads may be reduced as long as the total time is equal to, or greater than the time specified
in
table is based on the minimum timing for Tcyc (45ns). For microprocessors with slower busses, the
number of reads may be reduced as long as the total time is equal to, or greater than the time specified
in
. Note that dummy reads of the BYTE_TEST register are not required as long as the
minimum time period is met.
Table 3.3 LAN9118 Family PHY Control and Status Register
PHY CONTROL AND STATUS REGISTERS
INDEX
(IN DECIMAL)
REGISTER NAME
0
Basic Control Register
1
Basic Status Register
2
PHY Identifier 1
3
PHY Identifier 2
4
Auto-Negotiation Advertisement Register
5
Auto-Negotiation Link Partner Ability Register
6
Auto-Negotiation Expansion Register
17
Mode Control/Status Register
29
Interrupt Source Register
30
Interrupt Mask Register
31
PHY Special Control/Status Register