Cypress Semiconductor CapSense® Controller kit CY3280-BK1 CY3280-BK1 CY3280-BK1 Manual De Usuario
Los códigos de productos
CY3280-BK1
6
CY3280-BK1 Universal CapSense Controller Quick Start, Doc. # 001-37959 Rev. **
Getting Started
Additional CY3280-BK1 Universal CapSense Controller CD Content
■
Example projects for PSoC Express and PSoC Designer
■
Hardware schematics and gerber files
■
CY3240-I2USB software installer and documentation
CapSense Best Practices
The Universal CapSense Controller has been created using the best practices for CapSense lay out.
To enable universality and development of the kit and its projects, certain design elements have
been changed from what is recommended for final products. Below is a list of the design features in
the Universal CapSense Controller and what to change for final products.
To enable universality and development of the kit and its projects, certain design elements have
been changed from what is recommended for final products. Below is a list of the design features in
the Universal CapSense Controller and what to change for final products.
Design Feature
Reason
Impact
Recommended Change
Sensing traces
routed through a
connector to sen-
sors
routed through a
connector to sen-
sors
Buttons, sliders and LEDs
placed on the module board to
all for greater flexibility with cus-
tom modules for development
and subsequent releases.
placed on the module board to
all for greater flexibility with cus-
tom modules for development
and subsequent releases.
Connectors increase the para-
sitic capacitance of the sensors,
effectively reducing their sensi-
tivity. Connectors also create
another path for noise to enter
the system.
sitic capacitance of the sensors,
effectively reducing their sensi-
tivity. Connectors also create
another path for noise to enter
the system.
Sensors and control circuitry
should be located on the same
printed circuit board. Lower par-
asitic capacitance by reducing
trace lengths.
should be located on the same
printed circuit board. Lower par-
asitic capacitance by reducing
trace lengths.
Sensing traces
routed to other
schematic elements
routed to other
schematic elements
Universality of the board
enabled by population/depopu-
lation of 0-ohm resistors
enabled by population/depopu-
lation of 0-ohm resistors
Solder pads of 0-ohm resistors
increase parasitic capacitance.
increase parasitic capacitance.
Route traces directly to sensing
elements. Use as few 0-ohm
resistors as possible
elements. Use as few 0-ohm
resistors as possible
Sensing traces
located on the top
layer
located on the top
layer
Using vias to route traces to bot-
tom of board and back to con-
nector increases parasitic
capacitance.
tom of board and back to con-
nector increases parasitic
capacitance.
Possible noise sensitivity to
stimulus on top side of board.
Finger presses on routing of
control board can lead to sensor
activation.
stimulus on top side of board.
Finger presses on routing of
control board can lead to sensor
activation.
Route sensing traces on non-
user side of printed circuit
board. Route sensing traces as
far from noise sources as possi-
ble.
user side of printed circuit
board. Route sensing traces as
far from noise sources as possi-
ble.
Several regulators
used, including a
variable regulator
used, including a
variable regulator
Demonstration of CapSense at
several voltages.
several voltages.
Global and User Module param-
eters may need to be verified
with changing power supply.
eters may need to be verified
with changing power supply.
Supply one regulated voltage to
PSoC.
PSoC.
Test point on CMOD Accessibility of charge/dis-
charge waveforms
A test point increases noise sen-
sitivity by acting as an antenna.
sitivity by acting as an antenna.
Solder-pad test points for leads
offer better noise immunity if test
points are required.
offer better noise immunity if test
points are required.
GND spacing is
generalized for
noise immunity and
sensitivity
generalized for
noise immunity and
sensitivity
Universality of kit required mid-
dle-ground on many parameters
dle-ground on many parameters
Design is not optimized for high-
noise or very thick overlays
noise or very thick overlays
Increase spacing for thicker
overlays and better sensitivity.
Decrease spacing for greater
noise immunity
overlays and better sensitivity.
Decrease spacing for greater
noise immunity
Connection to shield
electrode is through
a jumper (module -
J2)
electrode is through
a jumper (module -
J2)
Flexibility of module boards for
both CSD and CSA control
boards
both CSD and CSA control
boards
Higher resistance paths can
impair performance of shield
electrode in CSD projects
impair performance of shield
electrode in CSD projects
Dedicated trace for shield elec-
trode. Remove jumpers wher-
ever possible
trode. Remove jumpers wher-
ever possible
ESD protection cir-
cuitry is not included
cuitry is not included
Development/evaluation plat-
form without consistent overlay
is inherently vulnerable to ESD
events
form without consistent overlay
is inherently vulnerable to ESD
events
Direct or air-separated ESD
testing may impair operation or
damage circuitry. +/-2kV limit on
PSoC pins (see datasheet).
testing may impair operation or
damage circuitry. +/-2kV limit on
PSoC pins (see datasheet).
Include an overlay and ESD pro-
tection circuitry
tection circuitry
UM Parameters set
to supplied overlay
thicknesses
to supplied overlay
thicknesses
Projects optimized for supplied
hardware
hardware
Sensitivity may not be high
enough for very thicker overlays
enough for very thicker overlays
Thicker overlays may require
verification of parameters to
ensure proper operation
verification of parameters to
ensure proper operation
Unused pins are not
routed directly to
GND
routed directly to
GND
Pins brought out to connector
for subsequent modules or cus-
tom designs
for subsequent modules or cus-
tom designs
Possible noise path
Tie unused sensing traces
directly to ground
directly to ground
0-ohm Resistors
populated through-
out
populated through-
out
Universality of the board
enabled by population/depopu-
lation of 0-ohm resistors
enabled by population/depopu-
lation of 0-ohm resistors
Solder pads of 0-ohm resistors
increase parasitic capacitance
increase parasitic capacitance
Route traces directly to sensing
elements. Use as few 0-ohm
resistors as possible
elements. Use as few 0-ohm
resistors as possible