STMicroelectronics M95M02-DRMN6TP Memory IC M95M02-DRMN6TP Hoja De Datos
Los códigos de productos
M95M02-DRMN6TP
Instructions
M95M02-DR
DocID18203 Rev 8
Figure 9. Write Disable (WRDI) sequence
6.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction is used to read the Status Register. The
Status Register may be read at any time, even while a Write or Write Status Register cycle is
in progress. When one of these cycles is in progress, it is recommended to check the Write
In Progress (WIP) bit before sending a new instruction to the device. It is also possible to
read the Status Register continuously, as shown in
Status Register may be read at any time, even while a Write or Write Status Register cycle is
in progress. When one of these cycles is in progress, it is recommended to check the Write
In Progress (WIP) bit before sending a new instruction to the device. It is also possible to
read the Status Register continuously, as shown in
Figure 10. Read Status Register (RDSR) sequence
The status and control bits of the Status Register are as follows:
6.3.1 WIP
bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such
cycle is in progress.
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such
cycle is in progress.
C
D
AI03750D
S
Q
2
1
3
4
5
6
7
High Impedance
0
Instruction
C
D
S
2
1
3
4
5
6
7
8
9 10 11 12 13 14 15
Instruction
0
AI02031E
Q
7
6
5
4
3
2
1
0
Status Register Out
High Impedance
MSB
7
6
5
4
3
2
1
0
Status Register Out
MSB
7