STMicroelectronics M95M02-DRMN6TP Memory IC Manuales de usuario

Tabla de contenidos

• 1 Description

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  • Figure 1. Logic diagram

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  • Table 1. Signal names

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  • Figure 2. 8-pin package connections (top view)

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  • Figure 3. WLCSP connections (bump side view)

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• 2 Memory organization

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  • Figure 4. Block diagram

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• 3 Signal description

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  • 3.1 Serial Data Output (Q)

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  • 3.2 Serial Data Input (D)

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  • 3.3 Serial Clock (C)

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  • 3.4 Chip Select (S)

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  • 3.5 Hold (HOLD)

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  • 3.6 Write Protect (W)

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  • 3.7 VCC supply voltage

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  • 3.8 VSS ground

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• 4 Connecting to the SPI bus

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  • Figure 5. Bus master and memory devices on the SPI bus

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  • 4.1 SPI modes

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    • Figure 6. SPI modes supported

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• 5 Operating features

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  • 5.1 Supply voltage (VCC)

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    • 5.1.1 Operating supply voltage VCC

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    • 5.1.2 Device reset

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    • 5.1.3 Power-up conditions

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    • 5.1.4 Power-down

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  • 5.2 Active Power and Standby Power modes

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  • 5.3 Hold condition

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    • Figure 7. Hold condition activation

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  • 5.4 Status Register

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  • 5.5 Data protection and protocol control

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    • Table 2. Write-protected block size

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• 6 Instructions

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  • Table 3. M95M02-DR instruction set

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  • 6.1 Write Enable (WREN)

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    • Figure 8. Write Enable (WREN) sequence

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  • 6.2 Write Disable (WRDI)

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    • Figure 9. Write Disable (WRDI) sequence

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  • 6.3 Read Status Register (RDSR)

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    • Figure 10. Read Status Register (RDSR) sequence

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    • 6.3.1 WIP bit

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    • 6.3.2 WEL bit

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    • 6.3.3 BP1, BP0 bits

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    • 6.3.4 SRWD bit

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      • Table 4. Status Register format

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  • 6.4 Write Status Register (WRSR)

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    • Figure 11. Write Status Register (WRSR) sequence

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    • Table 5. Protection modes

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  • 6.5 Read from Memory Array (READ)

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    • Figure 12. Read from Memory Array (READ) sequence

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  • 6.6 Write to Memory Array (WRITE)

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    • Figure 13. Byte Write (WRITE) sequence

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    • Figure 14. Page Write (WRITE) sequence

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    • 6.6.1 Cycling with Error Correction Code (ECC)

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  • 6.7 Read Identification Page

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    • Figure 15. Read Identification Page sequence

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  • 6.8 Write Identification Page

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    • Figure 16. Write identification page sequence

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  • 6.9 Read Lock Status

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    • Figure 17. Read Lock Status sequence

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  • 6.10 Lock ID

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    • Figure 18. Lock ID sequence

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• 7 Power-up and delivery state

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  • 7.1 Power-up state

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  • 7.2 Initial delivery state

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• 8 Maximum rating

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  • Table 6. Absolute maximum ratings

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• 9 DC and AC parameters

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  • Table 7. Operating conditions (M95M02-DR, device grade 6)

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  • Table 8. AC measurement conditions

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  • Figure 19. AC measurement I/O waveform

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  • Table 9. Capacitance

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  • Table 10. Cycling performance by groups of four bytes

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  • Table 11. Memory cell data retention

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  • Table 12. DC characteristics

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  • Table 13. AC characteristics

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  • Figure 20. Serial input timing

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  • Figure 21. Hold timing

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  • Figure 22. Serial output timing

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• 10 Package mechanical data

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  • Figure 23. SO8N – 8-lead plastic small outline, 150 mils body width, package outline

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  • Table 14. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data

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  • Figure 24. M95M02-DRCS6TP/K, WLCSP standard package outline, bump side view

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  • Table 15. M95M02-DRCS6TP/K, WLCSP package mechanical data

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• 11 Part numbering

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  • Table 16. Ordering information scheme

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• 12 Revision history

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  • Table 17. Document revision history

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