STMicroelectronics M95M02-DRMN6TP Memory IC M95M02-DRMN6TP Hoja De Datos

DocID18203 Rev 8

The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. 
The only way to do this is to send a Write Enable instruction to the device.

As shown in 

, to send this instruction to the device, Chip Select (S) is driven low, 

and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then 
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven 
high.

One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction 
to the device.

As shown in 

, to send this instruction to the device, Chip Select (S) is driven low, 

and the bits of the instruction byte are shifted in, on Serial Data Input (D).

The device then enters a wait state. It waits for a the device to be deselected, by Chip Select 
(S) being driven high.

The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
•

Power-up

•

WRDI instruction execution

•

WRSR instruction completion

•

WRITE instruction completion.

C

D

AI02281E

S

Q

2

1

3

4

5

6

7

High Impedance

0

Instruction