STMicroelectronics M95M02-DRMN6TP Memory IC M95M02-DRMN6TP Hoja De Datos
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M95M02-DRMN6TP
DocID18203 Rev 8
M95M02-DR
Instructions
The protection features of the device are summarized in
.
When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W) input pin.
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W) input pin.
When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two
cases should be considered, depending on the state of the Write Protect (W) input pin:
•
cases should be considered, depending on the state of the Write Protect (W) input pin:
•
If Write Protect (W) is driven high, it is possible to write to the Status Register (provided
that the WEL bit has previously been set by a WREN instruction).
that the WEL bit has previously been set by a WREN instruction).
•
If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the WEL bit has previously been set by a WREN instruction. (Attempts to write to the
Status Register are rejected, and are not accepted for execution). As a consequence,
all the data bytes in the memory area, which are Software-protected (SPM) by the
Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected
against data modification.
the WEL bit has previously been set by a WREN instruction. (Attempts to write to the
Status Register are rejected, and are not accepted for execution). As a consequence,
all the data bytes in the memory area, which are Software-protected (SPM) by the
Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected
against data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered by:
•
entered by:
•
either setting the SRWD bit after driving the Write Protect (W) input pin low,
•
or driving the Write Protect (W) input pin low after setting the SRWD bit.
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to
pull high the Write Protect (W) input pin.
pull high the Write Protect (W) input pin.
If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode
(HPM) can never be activated, and only the Software-protected mode (SPM), using the
Block Protect (BP1, BP0) bits in the Status Register, can be used.
(HPM) can never be activated, and only the Software-protected mode (SPM), using the
Block Protect (BP1, BP0) bits in the Status Register, can be used.
Table 5. Protection modes
W
signal
SRWD
bit
Mode
Write protection of the
Status Register
Memory content
Protected area
(1)
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register. See
Unprotected area
1
0
Software-
protected
(SPM)
Status Register is writable
(if the WREN instruction
has set the WEL bit).
(if the WREN instruction
has set the WEL bit).
The values in the BP1
and BP0 bits can be
changed.
and BP0 bits can be
changed.
Write-protected
Ready to accept
Write instructions
Write instructions
0
0
1
1
0
1
Hardware-
protected
(HPM)
Status Register is
Hardware write-
protected.
Hardware write-
protected.
The values in the BP1
and BP0 bits cannot be
changed.
and BP0 bits cannot be
changed.
Write-protected
Ready to accept
Write instructions
Write instructions