STMicroelectronics M95M02-DRMN6TP Memory IC M95M02-DRMN6TP Hoja De Datos

DocID18203 Rev 8

          

In the case of 

, Chip Select (S) is driven high after the eighth bit of the data byte 

has been latched in, indicating that the instruction is being used to write a single byte. 
However, if Chip Select (S) continues to be driven low, as shown in 

, the next byte 

of input data is shifted in, so that more than a single byte, starting from the given address 
towards the end of the same page, can be written in a single internal Write cycle.

Each time a new data byte is shifted in, the least significant bits of the internal address 
counter are incremented. If more bytes are sent than will fit up to the end of the page, a 
condition known as “roll-over” occurs. In case of roll-over, the bytes exceeding the page size 
are overwritten from location 0 of the same page.

The instruction is not accepted, and is not executed, under the following conditions:
•

if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable 
instruction just before),

•

if a Write cycle is already in progress,

•

if the device has not been deselected, by driving high Chip Select (S), at a byte 
boundary (after the eighth bit, b0, of the last data byte that has been latched in),

•

if the addressed page is in the region protected by the Block Protect (BP1 and BP0) 
bits.

          

MS30905V1

C

D

S

Q

23

2

1

3

4

5

6

7

8

9 10

28 29 30 31 32 33 34 35

22 21

3

2

1

0

36 37 38

High impedance

Instruction

24-bit address

0

7

6

5

4

3

2

0

1

Data byte

39