Toshiba Xeon 2.8GHz UPG3843W Manual De Usuario
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UPG3843W
Intel® Xeon™ Processor with 512 KB L2 Cache
Datasheet
11
1.0
Introduction
The Intel
®
Xeon™ processor with 512 KB L2 cache is based on the Intel
®
NetBurst™ micro-
architecture, which operates at significantly higher clock speeds and delivers performance levels
that are significantly higher than previous generations of IA-32 processors. While based on the
Intel
that are significantly higher than previous generations of IA-32 processors. While based on the
Intel
NetBurst micro-architecture, it maintains the tradition of compatibility with IA-32 software.
The Intel
NetBurst micro-architecture features begin with innovative techniques that enhance
processor execution such as Hyper Pipelined Technology, a Rapid Execution Engine, Advanced
Dynamic Execution, enhanced Floating Point and Multimedia unit, and Streaming SIMD
Extensions 2 (SSE2). The Hyper Pipelined Technology doubles the pipeline depth in the processor,
allowing the processor to reach much higher core frequencies. The Rapid Execution Engine allows
the two integer ALUs in the processor to run at twice the core frequency, which allows many
integer instructions to execute in one half of the internal core clock period. The Advanced Dynamic
Execution improves speculative execution and branch prediction internal to the processor. The
floating point and multi-media units have been improved by making the registers 128 bits wide and
adding a separate register for data movement. Finally, SSE2 adds 144 new instructions for double-
precision floating point, SIMD integer, and memory management for improvements in video/
multimedia processing, secure transactions, and visual internet applications.
Dynamic Execution, enhanced Floating Point and Multimedia unit, and Streaming SIMD
Extensions 2 (SSE2). The Hyper Pipelined Technology doubles the pipeline depth in the processor,
allowing the processor to reach much higher core frequencies. The Rapid Execution Engine allows
the two integer ALUs in the processor to run at twice the core frequency, which allows many
integer instructions to execute in one half of the internal core clock period. The Advanced Dynamic
Execution improves speculative execution and branch prediction internal to the processor. The
floating point and multi-media units have been improved by making the registers 128 bits wide and
adding a separate register for data movement. Finally, SSE2 adds 144 new instructions for double-
precision floating point, SIMD integer, and memory management for improvements in video/
multimedia processing, secure transactions, and visual internet applications.
Also part of the Intel NetBurst micro-architecture, the front side bus and caches on the Intel Xeon
processor with 512 KB L2 cache provide tremendous throughput for server and workstation
workloads. The 400 MHz front side bus provides a high-bandwidth pipeline to the system memory
and I/O. It is a quad-pumped bus running off a 100 MHz front side bus clock making 3.2 Gigabytes
per second (3,200 Megabytes per second) data transfer rates possible. The Execution Trace Cache
is a level 1 cache that stores approximately twelve thousand decoded micro-operations, which
removes the decoder latency from the main execution path and increases performance. The
Advanced Transfer Cache is a 512 KB on-die level 2 cache running at the speed of the processor
core providing increased bandwidth over previous micro-architectures.
processor with 512 KB L2 cache provide tremendous throughput for server and workstation
workloads. The 400 MHz front side bus provides a high-bandwidth pipeline to the system memory
and I/O. It is a quad-pumped bus running off a 100 MHz front side bus clock making 3.2 Gigabytes
per second (3,200 Megabytes per second) data transfer rates possible. The Execution Trace Cache
is a level 1 cache that stores approximately twelve thousand decoded micro-operations, which
removes the decoder latency from the main execution path and increases performance. The
Advanced Transfer Cache is a 512 KB on-die level 2 cache running at the speed of the processor
core providing increased bandwidth over previous micro-architectures.
In addition to the Intel NetBurst micro-architecture, the Intel Xeon processor with 512 KB L2
cache includes a groundbreaking new technology called Hyper-Threading technology, which
enables multi-threaded software to execute tasks in parallel within the processor resulting in a more
efficient, simultaneous use of processor resources. Server applications can realize increased
performance from Hyper-Threading technology today, while workstation applications are expected
to benefit from Hyper-Threading technology in the future through software and processor
evolution. The combination of Intel NetBurst micro-architecture and Hyper-Threading technology
delivers outstanding performance, throughput, and headroom for peak software workloads
resulting in faster response times and improved scalability.
cache includes a groundbreaking new technology called Hyper-Threading technology, which
enables multi-threaded software to execute tasks in parallel within the processor resulting in a more
efficient, simultaneous use of processor resources. Server applications can realize increased
performance from Hyper-Threading technology today, while workstation applications are expected
to benefit from Hyper-Threading technology in the future through software and processor
evolution. The combination of Intel NetBurst micro-architecture and Hyper-Threading technology
delivers outstanding performance, throughput, and headroom for peak software workloads
resulting in faster response times and improved scalability.
The Intel
Xeon processor with 512 KB L2 cache is intended for high performance workstation and
server systems with up to two processors on a single bus. The processor supports both uni- and
dual-processor designs and includes manageability features. Components of the manageability
features include an OEM EEPROM and Processor Information ROM that are accessible through a
SMBus interface. The Processor Information ROM includes information that is relevant to the
particular processor and system in which it is installed.
dual-processor designs and includes manageability features. Components of the manageability
features include an OEM EEPROM and Processor Information ROM that are accessible through a
SMBus interface. The Processor Information ROM includes information that is relevant to the
particular processor and system in which it is installed.
The Intel
Xeon processor with 512 KB L2 cache is packaged in a 603-pin interposer micro-PGA
(INT-mPGA) package, and utilizes a surface mount ZIF socket with 603 pins. Mechanical
components used for attaching thermal solutions to the baseboard should have a high degree of
commonality with the thermal solution components enabled for the Intel Xeon processor.
Heatsinks and retention mechanisms have been designed with manufacturability as a high priority.
Hence, mechanical assembly can be completed from the top of the baseboard.
components used for attaching thermal solutions to the baseboard should have a high degree of
commonality with the thermal solution components enabled for the Intel Xeon processor.
Heatsinks and retention mechanisms have been designed with manufacturability as a high priority.
Hence, mechanical assembly can be completed from the top of the baseboard.