Toshiba Xeon 2.8GHz UPG3843W Manual De Usuario
Los códigos de productos
UPG3843W
Intel® Xeon™ Processor with 512 KB L2 Cache
Datasheet
13
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Integrated Heat Spreader (IHS) - The surface used to attach a heatsink or other thermal
solution to the processor.
solution to the processor.
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Interposer - The structure on which the processor core package and I/O pins are mounted.
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OEM - Original Equipment Manufacturer.
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Processor core - The processor’s execution engine. All AC timing and signal integrity
specifications are to the pads of the processor core.
specifications are to the pads of the processor core.
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Processor Information ROM (PIROM) - An SMBus accessible memory device located on
the processor interposer. This memory device contains information regarding the processor’s
features. This device is shared with a scratch EEPROM. The PIROM is programmed during
the manufacturing and is write-protected. See
the processor interposer. This memory device contains information regarding the processor’s
features. This device is shared with a scratch EEPROM. The PIROM is programmed during
the manufacturing and is write-protected. See
for details on the PIROM.
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Retention mechanism - The support components that are mounted through the baseboard to
the chassis to provide mechanical retention for the processor and heatsink assembly.
the chassis to provide mechanical retention for the processor and heatsink assembly.
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Scratch EEPROM (Electrically Erasable, Programmable Read-Only Memory) - An
SMBus accessible memory device located on the processor interposer. This memory device
can be used by the OEM to store information useful for system management. See
SMBus accessible memory device located on the processor interposer. This memory device
can be used by the OEM to store information useful for system management. See
for details on the Scratch EEPROM.
•
SMBus - System Management Bus. A two-wire interface through which simple system and
power management related devices can communicate with the rest of the system. It is based on
the principals of the operation of the I2C two-wire serial bus from Philips Semiconductor.
power management related devices can communicate with the rest of the system. It is based on
the principals of the operation of the I2C two-wire serial bus from Philips Semiconductor.
Note: “I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a
subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/
protocol or the SMBus bus/protocol may require licenses from various entities, including
Philips Electronics N.V. and North American Philips Corporation.”
subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/
protocol or the SMBus bus/protocol may require licenses from various entities, including
Philips Electronics N.V. and North American Philips Corporation.”
•
Symmetric Agent - A symmetric agent is a processor which shares the same I/O subsystem
and memory array, and runs the same operating system as another processor in a system.
Systems using symmetric agents are known as Symmetric Multiprocessing (SMP) systems.
Intel
and memory array, and runs the same operating system as another processor in a system.
Systems using symmetric agents are known as Symmetric Multiprocessing (SMP) systems.
Intel
®
Xeon™ (DP - Dual Processor) processors should only be used in SMP systems which
have two or fewer symmetric agents.
1.2
State of Data
The data contained in this document is subject to change. It is the best information that Intel is able
to provide at the publication date of this document.
to provide at the publication date of this document.