Toshiba Xeon 2.8GHz UPG3843W Manual De Usuario

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Intel® Xeon™ Processor with 512 KB L2 Cache
14
Datasheet
1.3
References
The reader of this specification should also be familiar with material and concepts presented in the
following documents:.
NOTES:
1. Contact your Intel representative for the latest revision of documents without order numbers.
2. The signal integrity models are in IBIS format.
Document
Intel Order Number
1
AP-485, Intel® Processor Identification and the CPUID Instruction
241618
 IA-32 Intel ® Architecture Software Developer's Manual 
• Volume I: Basic Architecture
• Volume II: Instruction Set Reference
• Volume III: System Programming Guide
245470
245471
245472
Intel ® Xeon
TM
Processor and Intel
®
 860 Chipset Platform Design Guide
298252
Intel® Xeon™ Processor Thermal Design Guidelines
298348
603 -Pin Socket Design Guidelines
249672
Intel® Xeon™ Processor Specification Update
249678
CK00 Clock Synthesizer/Driver Design Guidelines
249206
VRM 9.0 DC-DC Converter Design Guidelines
249205
VRM 9.1 DC-DC Converter Design Guidelines
298646
Dual Intel® Xeon
TM
 Processor Voltage Regulator Down (VRD) Design 
Guidelines
298644
ITP700 Debug Port Design Guide
249679
Intel® Xeon™ Processor with 512 KB L2 Cache System Compatibility 
Guidelines
298645
Intel® Xeon™ Processor with 512 KB L2 Cache Signal Integrity Models
http://developer.intel.com
2
Intel® Xeon™ Processor with 512 KB L2 Cache Mechanical Models in ProE* 
Format
http://developer.intel.com
Intel® Xeon™ Processor with 512 KB L2 Cache Mechanical Models in IGES* 
Format
http://developer.intel.com
Intel® Xeon™ Processor with 512 KB L2 Cache Thermal Models (FloTherm* 
and ICEPAK* format)
http://developer.intel.com
Intel® Xeon™ Processor with 512 KB L2 Cache Core Boundary Scan 
Descriptor Language (BSDL) Model
http://developer.intel.com
System Management Bus Specification, rev 1.1
http://www.sbs-forum.org/
smbus
Wired for Management 2.0 Design Guide
http://developer.intel.com
Boxed Integration Notes
http://support.intel.com/
support/processors/xeon