Toshiba Xeon 2.8GHz UPG3843W Manual De Usuario

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9. SM_Vcc is required for correct VID logic operation of the Intel

®

 Xeon™ processor with 512 KB L2 cache.

Refer to 

 for details.

The Intel

®

 Xeon™ processor with 512 KB L2 cache does not utilize CMOS voltage levels on any

signals that connect to the processor silicon. As a result, legacy input signals such as A20M#,
IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# utilize GTL+ input
buffers. Legacy output FERR#/PBE# and other non-AGTL+ signals IERR#, THERMTRIP# and
PROCHOT# utilize GTL+ output buffers. All of these asynchronous GTL+ signals follow the same
DC requirements as AGTL+ signals, however the outputs are not driven high (during the logical 0-
to-1 transition) by the processor (the major difference between GTL+ and AGTL+). Asynchronous
GTL+ signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all
of the asynchronous GTL+ signals are required to be asserted for at least two BCLKs in order for
the processor to recognize them. See 

 and 

 for the DC and AC specifications for

the asynchronous GTL+ signal groups.

SMBus signals are derived from components mounted on the processor interposer along with the
processor silicon. The required SM_V

CC

 for these signals is 3.3 volts. See 

 for further

details. 

 lists the processor’s maximum environmental stress ratings. Functional operation at the

absolute maximum and minimum is neither implied nor guaranteed. The processor should not
receive a clock while subjected to these conditions. Functional operating parameters are listed in
the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.
Furthermore, although the processor contains protective circuitry to resist damage from static
electric discharge, one should always take precautions to avoid high static voltages or electric
fields.

1. This rating applies to any pin of the processor.
2. Contact Intel for storage requirements in excess of one year.

T

STORAGE

Processor storage temperature

-40

85

°C

2

V

CC

Any processor supply voltage with 
respect to V

SS

-0.3

1.75

V

1

V

inAGTL+

AGTL+ buffer DC input voltage with 
respect to V

SS

-0.1

1.75

V

V

inGTL+

Async GTL+ buffer DC input voltage 
with respect to Vss

-0.1

1.75

V

V

inSMBus

SMBus buffer DC input voltage with 
respect to Vss

-0.3

6.0

V

I

VID

Max VID pin current

5

mA