Toshiba Xeon 2.8GHz UPG3843W Manual De Usuario

45

This section documents signal quality metrics used to derive topology and routing guidelines
through simulation. All specifications are made at the processor core (pad measurements).

Source synchronous data transfer requires the clean reception of data signals and their associated
strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage
swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be
tolerated since these phenomena may inadvertently advance receiver state machines. Excessive
signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and can
cause device failure if absolute voltage limits are exceeded. Additionally, overshoot and
undershoot can degrade timing due to the build up of inter-symbol interference (ISI) effects. For
these reasons, it is crucial that the designer assure acceptable signal quality across all systematic
variations encountered in volume manufacturing.

Specifications for signal quality are for measurements at the processor core only and are only
observable through simulation. The same is true for all front side bus AC timing specifications in

. Therefore, proper simulation of the processor front side bus is the only means to

verify proper timing and signal quality metrics.

 describes the signal quality specifications at the processor pads for the processor front

side bus clock (BCLK) signals. 

 describes the signal quality waveform for the front side

bus clock at the processor pads. 

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute 

voltage the BCLK signal can dip back to after passing the V

IH

 (rising) or V

IL

 

(falling) voltage limits. This 

specification is an absolute value.

BCLK[1:0] Overshoot

N/A

0.30

V

1

BCLK[1:0] Undershoot

N/A

0.30

V

1

BCLK[1:0] Ringback Margin

0.20

N/A

V

1

BCLK[1:0] Threshold Region

N/A

0.10

V

1, 2