Toshiba Xeon 2.8GHz UPG3843W Manual De Usuario
Los códigos de productos
UPG3843W
Intel® Xeon™ Processor with 512 KB L2 Cache
Datasheet
47
Table 23. Ringback Specifications for TAP Buffers
NOTES:
1. All signal integrity specifications are measured at the processor core (pads).
2. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
3. Specifications are for the edge rate of 0.3 - 4.0 V/nS.
4. All values specified by design characterization.
5. Please see section 3.3 for maximum allowable overshoot.
2. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
3. Specifications are for the edge rate of 0.3 - 4.0 V/nS.
4. All values specified by design characterization.
5. Please see section 3.3 for maximum allowable overshoot.
Signal
Group
Group
Transition
Maximum Ringback
(with Input Diodes Present)
Threshold
Unit
Figure
Notes
TAP and
PWRGOO
D
PWRGOO
D
L
→
H
V
T+(max) TO
V
T-(max)
V
T+(max)
V
1, 2, 3, 4, 5
TAP and
PWRGOO
D
PWRGOO
D
H
→
L
V
T-(min) TO
V
T+(min)
V
T-(min)
V
1, 2, 3, 4, 5
Figure 21. Low-to-High Front Side Bus Receiver Ringback Tolerance for AGTL+ and
Asynchronous GTL+ Buffers
GTLREF
V
CC
Noise Margin
+10% Vcc
-10% Vcc
V
SS