Toshiba Xeon 2.8GHz UPG3843W Manual De Usuario
Los códigos de productos
UPG3843W
Intel® Xeon™ Processor with 512 KB L2 Cache
48
Datasheet
Figure 23. Low-to-High Front Side Bus Receiver Ringback Tolerance for PWRGOOD TAP
Buffers
Figure 22. High-to-Low Front Side Bus Receiver Ringback Tolerance for AGTL+ and
Asynchronous GTL+ Buffers
GTLREF
V
CC
Noise Margin
+10% Vcc
V
SS
-10% Vcc
0.5 * Vcc
Vt+ (min)
Vt+ (max)
Vt- (max)
Vcc
Allowable Ringback
Vss
Threshold Region to switch
receiver to a logic 1.