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ATSAM4S-XPLD
290
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
18.4.2 Slow Clock Generator
The Supply Controller embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as the
VDDIO is supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the embedded
RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100
VDDIO is supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the embedded
RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100
μs).
The user can select the crystal oscillator to be the source of the slow clock, as it provides a more accurate frequency.
The command is made by writing the Supply Controller Control Register (SUPC_CR) with the XTALSEL bit at 1.This
results in a sequence which first configures the PIO lines multiplexed with XIN32 and XOUT32 to be driven by the
oscillator, then enables the crystal oscillator, then counts a number of slow RC oscillator clock periods to cover the start-
up time of the crystal oscillator (refer to electrical characteristics for details of 32KHz crystal oscillator start-up time), then
switches the slow clock on the output of the crystal oscillator and then disables the RC oscillator to save power. The
switching time may vary according to the slow RC oscillator clock frequency range. The switch of the slow clock source is
glitch free. The OSCSEL bit of the Supply Controller Status Register (SUPC_SR) allows knowing when the switch
sequence is done.
The command is made by writing the Supply Controller Control Register (SUPC_CR) with the XTALSEL bit at 1.This
results in a sequence which first configures the PIO lines multiplexed with XIN32 and XOUT32 to be driven by the
oscillator, then enables the crystal oscillator, then counts a number of slow RC oscillator clock periods to cover the start-
up time of the crystal oscillator (refer to electrical characteristics for details of 32KHz crystal oscillator start-up time), then
switches the slow clock on the output of the crystal oscillator and then disables the RC oscillator to save power. The
switching time may vary according to the slow RC oscillator clock frequency range. The switch of the slow clock source is
glitch free. The OSCSEL bit of the Supply Controller Status Register (SUPC_SR) allows knowing when the switch
sequence is done.
Coming back on the RC oscillator is only possible by shutting down the VDDIO power supply.
If the user does not need the crystal oscillator, the XIN32 and XOUT32 pins should be left unconnected.
The user can also set the crystal oscillator in bypass mode instead of connecting a crystal. In this case, the user has to
provide the external clock signal on XIN32. The input characteristics of the XIN32 pin are given in the product electrical
characteristics section. In order to set the bypass mode, the OSCBYPASS bit of the Supply Controller Mode Register
(SUPC_MR) needs to be set at 1.
provide the external clock signal on XIN32. The input characteristics of the XIN32 pin are given in the product electrical
characteristics section. In order to set the bypass mode, the OSCBYPASS bit of the Supply Controller Mode Register
(SUPC_MR) needs to be set at 1.
18.4.3 Voltage Regulator Control/Backup Low Power Mode
The Supply Controller can be used to control the embedded voltage regulator.
The voltage regulator automatically adapts its quiescent current depending on the required load current. Please refer to
the electrical characteristics section.
the electrical characteristics section.
The programmer can switch off the voltage regulator, and thus put the device in Backup mode, by writing the Supply
Controller Control Register (SUPC_CR) with the VROFF bit at 1.
Controller Control Register (SUPC_CR) with the VROFF bit at 1.
This asserts the vddcore_nreset signal after the write resynchronization time which lasts, in the worse case, two slow
clock cycles. Once the vddcore_nreset signal is asserted, the processor and the peripherals are stopped one slow clock
cycle before the core power supply shuts off.
clock cycles. Once the vddcore_nreset signal is asserted, the processor and the peripherals are stopped one slow clock
cycle before the core power supply shuts off.
When the user does not use the internal voltage regulator and wants to supply VDDCORE by an external supply, it is
possible to disable the voltage regulator. Note that it is different from the Backup mode. Depending on the application,
disabling the voltage regulator can reduce power consumption as the voltage regulator input (VDDIN) is shared with the
ADC and DAC. This is done through ONREG bit in SUPC_MR.
possible to disable the voltage regulator. Note that it is different from the Backup mode. Depending on the application,
disabling the voltage regulator can reduce power consumption as the voltage regulator input (VDDIN) is shared with the
ADC and DAC. This is done through ONREG bit in SUPC_MR.