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SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
18.4.4 Supply Monitor
The Supply Controller embeds a supply monitor which is located in the VDDIO Power Supply and which monitors VDDIO
power supply.
The supply monitor can be used to prevent the processor from falling into an unpredictable state if the Main power supply
drops below a certain level.
The threshold of the supply monitor is programmable. It can be selected from 1.9V to 3.4V by steps of 100 mV. This
threshold is programmed in the SMTH field of the Supply Controller Supply Monitor Mode Register (SUPC_SMMR).
The supply monitor can also be enabled during one slow clock period on every one of either 32, 256 or 2048 slow clock
periods, according to the choice of the user. This can be configured by programming the SMSMPL field in SUPC_SMMR.
Enabling the supply monitor for such reduced times allows to divide the typical supply monitor power consumption
respectively by factors of 32, 256 or 2048, if the user does not need a continuous monitoring of the VDDIO power supply.
A supply monitor detection can either generate a reset of the core power supply or a wake up of the core power supply.
Generating a core reset when a supply monitor detection occurs is enabled by writing the SMRSTEN bit to 1 in
SUPC_SMMR. 
Waking up the core power supply when a supply monitor detection occurs can be enabled by programming the SMEN bit
to 1 in the Supply Controller Wake Up Mode Register (SUPC_WUMR).
The Supply Controller provides two status bits in the Supply Controller Status Register for the supply monitor which
allows to determine whether the last wake up was due to the supply monitor:
The SMOS bit provides real time information, which is updated at each measurement cycle or updated at each 
Slow Clock cycle, if the measurement is continuous.
The SMS bit provides saved information and shows a supply monitor detection has occurred since the last read of 
SUPC_SR.
The SMS bit can generate an interrupt if the SMIEN bit is set to 1 in the Supply Controller Supply Monitor Mode Register
(SUPC_SMMR).
Figure 18-2. Supply Monitor Status Bit and Associated Interrupt
Supply Monitor ON
3.3 V
0 V
Threshold
SMS and SUPC interrupt
Read SUPC_SR
Periodic Sampling
Continuous Sampling (SMSMPL = 1)