Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

As soon as the backup voltage VDDIO rises, the RC oscillator is powered up and the zero-power power-on reset cell
maintains its output low as long as VDDIO has not reached its target voltage. During this time, the Supply Controller is
entirely reset. When the VDDIO voltage becomes valid and zero-power power-on reset signal is released, a counter is
started for 5 slow clock cycles. This is the time it takes for the 32 kHz RC oscillator to stabilize.

After this time, the voltage regulator is enabled. The core power supply rises and the brownout detector provides the
bodcore_in signal as soon as the core voltage VDDCORE is valid. This results in releasing the vddcore_nreset signal to
the Reset Controller after the bodcore_in signal has been confirmed as being valid for at least one slow clock cycle.

Zero-Power Power-On

Reset Cell output

22 - 42 kHz RC

Oscillator output

Fast RC

Oscillator output

Backup Power Supply

vr_on

bodcore_in

vddcore_nreset

NRST

(no ext. drive assumed)

proc_nreset

Note: After “proc_nreset” rising, the core starts fetching instructions from Flash at 4 MHz.

periph_nreset

7 x Slow Clock Cycles

3 x Slow Clock

Cycles

2 x Slow Clock

Cycles

6.5 x Slow Clock

Cycles

T

ON

 Voltage

Regulator

Zero-Power POR

Core Power Supply

RSTC.ERSTL

(5 for startup slow RC + 2 for synchro.)

default = 2