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ATSAM4S-XPLD
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SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
20.4.3.6 Calibration Bit
Calibration bits do not interfere with the embedded Flash memory plane.
It is impossible to modify the calibration bits.
The status of calibration bits can be returned by the Enhanced Embedded Flash Controller (EEFC). The sequence is:
Issue the Get CALIB Bit command by writing the Flash Command Register with GCALB (see
FARG field is meaningless.
Calibration bits can be read by the software application in the EEFC_FRR register. The first word read
corresponds to the 32 first calibration bits, following reads provide the next 32 calibration bits as long as it is
meaningful. Extra reads to the EEFC_FRR register return 0.
corresponds to the 32 first calibration bits, following reads provide the next 32 calibration bits as long as it is
meaningful. Extra reads to the EEFC_FRR register return 0.
The 4/8/12 MHz Fast RC oscillator is calibrated in production. This calibration can be read through the Get CALIB Bit
command. The table below shows the bit implementation for each frequency:
command. The table below shows the bit implementation for each frequency:
The RC calibration for 4 MHz is set to 1,000,000.
20.4.3.7 Security Bit Protection
When the security is enabled, access to the Flash, either through the JTAG/SWD interface or through the Fast Flash
Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.
Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.
The security bit is GPNVM0.
Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is performed.
When the security bit is deactivated, all accesses to the Flash are permitted.
When the security bit is deactivated, all accesses to the Flash are permitted.
20.4.3.8 Unique Identifier
Each part is programmed with a 128 bits Unique Identifier. It can be used to generate keys for example. For the
SAM3SD8, the unique ID is accessible on both memory planes.
SAM3SD8, the unique ID is accessible on both memory planes.
To read the Unique Identifier the sequence is:
Send the Start Read unique Identifier command (STUI) by writing the Flash Command Register with the STUI
command.
command.
When the Unique Identifier is ready to be read, the FRDY bit in the Flash Programming Status Register
(EEFC_FSR) falls.
(EEFC_FSR) falls.
The Unique Identifier is located in the first 128 bits of the Flash memory mapping, thus, at the address
0x00400000-0x004003FF
.
To stop the Unique Identifier mode, the user needs to send the Stop Read unique Identifier command (SPUI) by
writing the Flash Command Register with the SPUI command.
writing the Flash Command Register with the SPUI command.
When the Stop read Unique Identifier command (SPUI) has been performed, the FRDY bit in the Flash
Programming Status Register (EEFC_FSR) rises. If an interrupt was enabled by setting the FRDY bit in
EEFC_FMR, the interrupt line of the NVIC is activated.
Programming Status Register (EEFC_FSR) rises. If an interrupt was enabled by setting the FRDY bit in
EEFC_FMR, the interrupt line of the NVIC is activated.
Note that during the sequence, the software can not run out of Flash (or the second plane in case of dual plane).
RC Calibration Frequency
EEFC_FRR Bits
8 MHz output
[28 - 22]
12 MHz output
[38 - 32]