Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned
to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the address of the
page in memory, the LSB of address define the address of the data in the page as detailed in 

. 

With page mode memory devices, the first access to one page (t

pa

) takes longer than the subsequent accesses to the

page (t

sa

the first access within one page, and next accesses within the page. 

Note:

1.

“A” denotes the address bus of the memory device.

The NRD and NCS signals are held low during all read transfers, whatever the programmed values of the setup and hold
timings in the User Interface may be. Moreover, the NRD and NCS timings are identical. The pulse length of the first
access to the page is defined with the NCS_RD_PULSE field of the SMC_PULSE register. The pulse length of
subsequent accesses within the page are defined using the NRD_PULSE parameter.

In page mode, the programming of the read timings is described in 

:

Data Address in the Page

4 bytes

A[23:2]

A[1:0]

8 bytes

A[23:3]

A[2:0]

16 bytes

A[23:4]

A[3:0]

32 bytes

A[23:5]

A[4:0]

A[MSB]

NCS

MCK

NRD

D[7:0]

NCS_RD_PULSE

NRD_PULSE

NRD_PULSE

tsa

tpa

tsa

A[LSB]

READ_MODE

‘x’ No 

impact

NCS_RD_SETUP

‘x’ No 

impact

NCS_RD_PULSE

t

pa

Access time of first access to the page