Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven
by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically
32kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are
applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow
clock rate. When activated, the slow mode is active on all chip selects.

indicates the value of read and write parameters in slow clock mode.

When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high
clock rate, with the set of slow clock mode parameters.See 

fast enough to support such timings. 

A[23:0]

NCS

1

MCK

NWE

1

1

NWE_CYCLE = 3

A[23:0]

MCK

NRD

NRD_CYCLE = 2

1

1

NCS

SLOW CLOCK MODE WRITE

SLOW CLOCK MODE READ

NRD_SETUP

1

NWE_SETUP

1

NRD_PULSE

1

NWE_PULSE

1

NCS_RD_SETUP

0

NCS_WR_SETUP

0

NCS_RD_PULSE

2

NCS_WR_PULSE

3

NRD_CYCLE

2

NWE_CYCLE

3