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ATSAM4S-XPLD
419
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 26-29.Clock Rate Transition Occurs while the SMC is Performing a Write Operation
Figure 26-30.Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock
Mode
26.14 Asynchronous Page Mode
The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE
register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes.
register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes.
A[23:0]
NCS
1
MCK
NWE
1
1
NWE_CYCLE = 3
SLOW CLOCK MODE WRITE
Slow Clock Mode
internal signal from PMC
1
1
1
2
3
2
NWE_CYCLE = 7
NORMAL MODE WRITE
Slow clock mode
transition is detected:
Reload Configuration Wait State
This write cycle finishes with the slow clock mode set
of parameters after the clock rate transition
SLOW CLOCK MODE WRITE
A[23:0]
NCS
1
MCK
NWE
1
1
SLOW CLOCK MODE WRITE
Slow Clock Mode
internal signal from PMC
2
3
2
NORMAL MODE WRITE
IDLE STATE
Reload Configuration
Wait State