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ATSAM4S-XPLD
438
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
27.5
Peripheral DMA Controller (PDC) User Interface
Note:
1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the
user according to the function and the desired peripheral.)
Table 27-2. Register Mapping
Offset
Register
Name
Access
Reset
0x00
Receive Pointer Register
Read-write
0
0x04
Receive Counter Register
PERIPH_RCR
Read-write
0
0x08
Transmit Pointer Register
PERIPH_TPR
Read-write
0
0x0C
Transmit Counter Register
PERIPH_TCR
Read-write
0
0x10
Receive Next Pointer Register
PERIPH_RNPR
Read-write
0
0x14
Receive Next Counter Register
PERIPH_RNCR
Read-write
0
0x18
Transmit Next Pointer Register
PERIPH_TNPR
Read-write
0
0x1C
Transmit Next Counter Register
PERIPH_TNCR
Read-write
0
0x20
Transfer Control Register
PERIPH_PTCR
Write-only
0
0x24
Transfer Status Register
PERIPH_PTSR
Read-only
0