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ATSAM4S-XPLD
436
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
27.4.3 Transfer Counters
Each channel has two 16-bit counters, one for current transfer and the other one for next transfer. These counters define
the size of data to be transferred by the channel. The current transfer counter is decremented first as the data addressed
by current memory pointer starts to be transferred. When the current transfer counter reaches zero, the channel checks
its next transfer counter. If the value of next counter is zero, the channel stops transferring data and sets the appropriate
flag. But if the next counter value is greater then zero, the values of the next pointer/next counter are copied into the
current pointer/current counter and the channel resumes the transfer whereas next pointer/next counter get zero/zero as
values. At the end of this transfer the PDC channel sets the appropriate flags in the Peripheral Status Register.
the size of data to be transferred by the channel. The current transfer counter is decremented first as the data addressed
by current memory pointer starts to be transferred. When the current transfer counter reaches zero, the channel checks
its next transfer counter. If the value of next counter is zero, the channel stops transferring data and sets the appropriate
flag. But if the next counter value is greater then zero, the values of the next pointer/next counter are copied into the
current pointer/current counter and the channel resumes the transfer whereas next pointer/next counter get zero/zero as
values. At the end of this transfer the PDC channel sets the appropriate flags in the Peripheral Status Register.
The following list gives an overview of how status register flags behave depending on the counters’ values:
ENDRX flag is set when the PERIPH_RCR register reaches zero.
RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero.
ENDTX flag is set when the PERIPH_TCR register reaches zero.
TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero.
These status flags are described in the Peripheral Status Register.
27.4.4 Data Transfers
The serial peripheral triggers its associated PDC channels’ transfers using transmit enable (TXEN) and receive enable
(RXEN) flags in the transfer control register integrated in the peripheral’s user interface.
(RXEN) flags in the transfer control register integrated in the peripheral’s user interface.
When the peripheral receives an external data, it sends a Receive Ready signal to its PDC receive channel which then
requests access to the Matrix. When access is granted, the PDC receive channel starts reading the peripheral Receive
Holding Register (RHR). The read data are stored in an internal buffer and then written to memory.
requests access to the Matrix. When access is granted, the PDC receive channel starts reading the peripheral Receive
Holding Register (RHR). The read data are stored in an internal buffer and then written to memory.
When the peripheral is about to send data, it sends a Transmit Ready to its PDC transmit channel which then requests
access to the Matrix. When access is granted, the PDC transmit channel reads data from memory and puts them to
Transmit Holding Register (THR) of its associated peripheral. The same peripheral sends data according to its
mechanism.
access to the Matrix. When access is granted, the PDC transmit channel reads data from memory and puts them to
Transmit Holding Register (THR) of its associated peripheral. The same peripheral sends data according to its
mechanism.