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ATSAM4S-XPLD
481
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.9PMC Clock Generator PLLA Register
Name:
CKGR_PLLAR
Address:
0x400E0428
Access:
Read-write
Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC.
Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
This register can only be written if the WPEN bit is cleared in
.
• DIVA: PLLA Front_End Divider
0 = Divider output is stuck at 0 and PLLA is disabled.
1 = Divider is bypassed (divide by 1) PLLA is enabled
2 up to 255 = clock is divided by DIVA
• PLLACOUNT: PLLA Counter
Specifies the number of Slow Clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• MULA: PLLA Multiplier
0 = The PLLA is deactivated (PLLA also disabled if DIVA = 0).
1 up to 80 = The PLLA Clock frequency is the PLLA input frequency multiplied by MULA + 1.
• ONE: Must Be Set to 1
Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
31
30
29
28
27
26
25
24
–
–
ONE
–
–
MULA
23
22
21
20
19
18
17
16
MULA
15
14
13
12
11
10
9
8
–
–
PLLACOUNT
7
6
5
4
3
2
1
0
DIVA