Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos
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ATSAM4S-XPLD
482
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.10PMC Clock Generator PLLB Register
Name:
CKGR_PLLBR
Address:
0x400E042C
Access:
Read-write
Possible limitations on PLLB input frequencies and multiplier factors should be checked before using the PMC.
This register can only be written if the WPEN bit is cleared in
.
• DIVB: PLLB Front-End Divider
0 = Divider output is stuck at 0 and PLLB is disabled.
1= Divider is bypassed (divide by 1)
2 up to 255 = clock is divided by DIVB
• PLLBCOUNT: PLLB Counter
Specifies the number of Slow Clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.
• MULB: PLLB Multiplier
0 = The PLLB is deactivated (PLLB also disabled if DIVB = 0).
1 up to 80 = The PLLB Clock frequency is the PLLB input frequency multiplied by MULB + 1.
31
30
29
28
27
26
25
24
–
–
–
–
–
MULB
23
22
21
20
19
18
17
16
MULB
15
14
13
12
11
10
9
8
–
–
PLLBCOUNT
7
6
5
4
3
2
1
0
DIVB