Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos
Los códigos de productos
ATSAM4S-XPLD
483
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.11PMC Master Clock Register
Name:
PMC_MCKR
Address:
0x400E0430
Access:
Read-write
This register can only be written if the WPEN bit is cleared in
.
• CSS: Master Clock Source Selection
• PRES: Processor Clock Prescaler
• PLLADIV2: PLLA Divisor by 2
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
PLLBDIV2
PLLADIV2
–
–
–
–
7
6
5
4
3
2
1
0
–
PRES
–
–
CSS
Value
Name
Description
0
SLOW_CLK
Slow Clock is selected
1
MAIN_CLK
Main Clock is selected
2
PLLA_CLK
PLLA Clock is selected
3
PLLB_CLK
PLLBClock is selected
Value
Name
Description
0
CLK_1
Selected clock
1
CLK_2
Selected clock divided by 2
2
CLK_4
Selected clock divided by 4
3
CLK_8
Selected clock divided by 8
4
CLK_16
Selected clock divided by 16
5
CLK_32
Selected clock divided by 32
6
CLK_64
Selected clock divided by 64
7
CLK_3
Selected clock divided by 3
PLLADIV2
PLLA Clock Division
0
PLLA clock frequency is divided by 1.
1
PLLA clock frequency is divided by 2.