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ATSAM4S-XPLD
50
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
12.4.1.3 Core Registers
Figure 12-2. Processor Core Registers
Notes: 1. Describes access type during program execution in thread mode and Handler mode. Debug access can differ.
2. An entry of Either means privileged and unprivileged software can access the register.
SP (R13)
LR (R14)
PC (R15)
R5
R6
R7
R0
R1
R3
R
4
R2
R10
R11
R12
R8
R9
Low registers
High registers
MSP
‡
PSP
‡
PSR
PRIMASK
FAULTMASK
BASEPRI
CONTROL
General-purpose registers
Stack Pointer
Link Register
Program Counter
Program status register
Exception mask registers
CONTROL register
Special registers
‡
Banked version of SP
Table 12-2. Core Processor Registers
Register
Name
Access
Required
Privilege
Privilege
Reset
General-purpose registers
R0-R12
Read-write
Either
Unknown
Stack Pointer
MSP
Read-write
Privileged
See description
Stack Pointer
PSP
Read-write
Either
Unknown
Link Register
LR
Read-write
Either
0xFFFFFFFF
Program Counter
PC
Read-write
Either
See description
Program Status Register
PSR
Read-write
Privileged
0x01000000
Application Program Status Register
APSR
Read-write
Either
0x00000000
Interrupt Program Status Register
IPSR
Read-only
Privileged
0x00000000
Execution Program Status Register
EPSR
Read-only
Privileged
0x01000000
Priority Mask Register
PRIMASK
Read-write
Privileged
0x00000000
Fault Mask Register
FAULTMASK
Read-write
Privileged
0x00000000
Base Priority Mask Register
BASEPRI
Read-write
Privileged
0x00000000
CONTROL register
CONTROL
Read-write
Privileged
0x00000000