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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

The PDC transfer size must be defined with the buffer size minus 2. The two remaining characters must be managed
without PDC to ensure that the exact number of bytes are received whatever the system bus latency conditions
encountered during the end of buffer transfer period.

1.

Initialize the receive PDC (memory pointers, transfer size - 2).

2.

Configure the master mode (DADR, CKDIV, etc.).

3.

Start the transfer by setting the PDC RXTEN bit.

4.

Wait for the PDC ENDRX Flag either by using polling method or ENDRX interrupt.

5.

Disable the PDC by setting the PDC RXDIS bit.

6.

Wait for the RXRDY flag in TWI_SR register

7.

Set the STOP command in TWI_CR

8.

Read the penultimate character in TWI_RHR

9.

Wait for the RXRDY flag in TWI_SR register

10. Read the last character in TWI_RHR

The TWI interface can perform a Quick Command:

1.

Configure the master mode (DADR, CKDIV, etc.).

2.

Write the MREAD bit in the TWI_MMR register at the value of the one-bit command to be sent.

3.

Start the transfer by setting the QUICK bit in the TWI_CR.

The following flowcharts shown in 

 and 

 give examples for read and write operations. A polling or

interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register
(TWI_IER) be configured first.

TXCOMP

TXRDY

Write QUICK command in TWI_CR

TWD

A

S

DADR

R/W

P