Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos
Los códigos de productos
ATSAM4S-XPLD
672
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
34.4
Product Dependencies
34.4.1 I/O Lines
The UART pins are multiplexed with PIO lines. The programmer must first configure the corresponding PIO Controller to
enable I/O line operations of the UART.
enable I/O line operations of the UART.
34.4.2 Power Management
The UART clock is controllable through the Power Management Controller. In this case, the programmer must first
configure the PMC to enable the UART clock. Usually, the peripheral identifier used for this purpose is 1.
configure the PMC to enable the UART clock. Usually, the peripheral identifier used for this purpose is 1.
34.4.3 Interrupt Source
The UART interrupt line is connected to one of the interrupt sources of the Interrupt Controller. Interrupt handling requires
programming of the Interrupt Controller before configuring the UART.
programming of the Interrupt Controller before configuring the UART.
34.5
UART Operations
The UART operates in asynchronous mode only and supports only 8-bit character handling (with parity). It has no clock
pin.
pin.
The UART is made up of a receiver and a transmitter that operate independently, and a common baud rate generator.
Receiver timeout and transmitter time guard are not implemented. However, all the implemented features are compatible
with those of a standard USART.
Receiver timeout and transmitter time guard are not implemented. However, all the implemented features are compatible
with those of a standard USART.
34.5.1 Baud Rate Generator
The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter.
The baud rate clock is the master clock divided by 16 times the value (CD) written in UART_BRGR (Baud Rate
Generator Register). If UART_BRGR is set to 0, the baud rate clock is disabled and the UART remains inactive.
The maximum allowable baud rate is Master Clock divided by 16. The minimum allowable baud rate is Master
Clock divided by (16 x 65536).
Generator Register). If UART_BRGR is set to 0, the baud rate clock is disabled and the UART remains inactive.
The maximum allowable baud rate is Master Clock divided by 16. The minimum allowable baud rate is Master
Clock divided by (16 x 65536).
Table 34-2. I/O Lines
Instance
Signal
I/O Line
Peripheral
UART0
URXD0
PA9
A
UART0
UTXD0
PA10
A
UART1
URXD1
PB2
A
UART1
UTXD1
PB3
A
Baud Rate
MCK
16
CD
×
-----------------------
=