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ATSAM4S-XPLD
673
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 34-2. Baud Rate Generator
34.5.2 Receiver
34.5.2.1 Receiver Reset, Enable and Disable
After device reset, the UART receiver is disabled and must be enabled before being used. The receiver can be enabled
by writing the control register UART_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start
bit.
by writing the control register UART_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start
bit.
The programmer can disable the receiver by writing UART_CR with the bit RXDIS at 1. If the receiver is waiting for a start
bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits
for the stop bit before actually stopping its operation.
bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits
for the stop bit before actually stopping its operation.
The programmer can also put the receiver in its reset state by writing UART_CR with the bit RSTRX at 1. In doing so, the
receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when
data is being processed, this data is lost.
receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when
data is being processed, this data is lost.
34.5.2.2 Start Detection and Data Sampling
The UART only supports asynchronous operations, and this affects only its receiver. The UART receiver detects the start
of a received character by sampling the URXD signal until it detects a valid start bit. A low level (space) on URXD is
interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud
rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit
period or shorter is ignored and the receiver continues to wait for a valid start bit.
of a received character by sampling the URXD signal until it detects a valid start bit. A low level (space) on URXD is
interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud
rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit
period or shorter is ignored and the receiver continues to wait for a valid start bit.
When a valid start bit has been detected, the receiver samples the URXD at the theoretical midpoint of each bit. It is
assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit
period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the
start bit was detected.
assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit
period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the
start bit was detected.
Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one.
Figure 34-3. Start Bit Detection
MCK
16-bit Counter
0
Baud Rate
Clock
CD
CD
OUT
Divide
by 16
0
1
>1
Receiver
Sampling Clock
Sampling Clock
Sampling Clock
URXD
True Start
Detection
D0
Baud Rate
Clock