Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos
Los códigos de productos
ATSAM4S-XPLD
861
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 38-5. Waveform Properties
38.6.2.3 2-bit Gray Up/Down Counter for Stepper Motor
It is possible to configure a couple of channels to provide a 2-bit gray count waveform on 2 outputs. Dead-Time
Generator and other downstream logic can be configured on these channels.
Generator and other downstream logic can be configured on these channels.
Up or down count mode can be configured on-the-fly by means of PWM_SMMR configuration registers.
When GCEN0 is set to 1, channels 0 and 1 outputs are driven with gray counter.
Channel x
slected clock
CHIDx(PWM_SR)
Center Aligned
CPRD(PWM_CPRDx)
CDTY(PWM_CDTYx)
PWM_CCNTx
Output Waveform OCx
CPOL(PWM_CMRx) = 0
Output Waveform OCx
CPOL(PWM_CMRx) = 1
Counter Event
CHIDx(PWM_ISR)
CES(PWM_CMRx) = 0
Left Aligned
CPRD(PWM_CPRDx)
CDTY(PWM_CDTYx)
PWM_CCNTx
Output Waveform OCx
CPOL(PWM_CMRx) = 0
Output Waveform OCx
CPOL(PWM_CMRx) = 1
CALG(PWM_CMRx) = 0
CALG(PWM_CMRx) = 1
Period
Period
CHIDx(PWM_ENA)
CHIDx(PWM_DIS)
Counter Event
CHIDx(PWM_ISR)
CES(PWM_CMRx) = 1
Counter Event
CHIDx(PWM_ISR)