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ATSAM4S-XPLD
865
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
When the fault protection is triggered on a channel, the fault protection mechanism resets the counter of this channel and
forces the channel outputs to the values defined by the fields FPVHx and FPVLx in the
forces the channel outputs to the values defined by the fields FPVHx and FPVLx in the
(PWM_FPV). The output forcing is made asynchronously to the channel counter.
CAUTION:
To prevent an unexpected activation of the status flag FSy in the PWM_FSR register, the FMODy bit can be set to
“1” only if the FPOLy bit has been previously configured to its final value.
“1” only if the FPOLy bit has been previously configured to its final value.
To prevent an unexpected activation of the Fault Protection on the channel x, the bit FPEx[y] can be set to “1” only
if the FPOLy bit has been previously configured to its final value.
if the FPOLy bit has been previously configured to its final value.
If a comparison unit is enabled (see
) and if a fault is triggered in the channel 0,
in this case the comparison cannot match.
As soon as the fault protection is triggered on a channel, an interrupt (different from the interrupt generated at the end of
the PWM period) can be generated but only if it is enabled and not masked. The interrupt is reset by reading the interrupt
status register, even if the fault which has caused the trigger of the fault protection is kept active.
the PWM period) can be generated but only if it is enabled and not masked. The interrupt is reset by reading the interrupt
status register, even if the fault which has caused the trigger of the fault protection is kept active.
38.6.2.7 Synchronous Channels
Some channels can be linked together as synchronous channels. They have the same source clock, the same period,
the same alignment and are started together. In this way, their counters are synchronized together.
the same alignment and are started together. In this way, their counters are synchronized together.
The synchronous channels are defined by the SYNCx bits in the
(PWM_SCM).
Only one group of synchronous channels is allowed.
When a channel is defined as a synchronous channel, the channel 0 is automatically defined as a synchronous channel
too, because the channel 0 counter configuration is used by all the synchronous channels.
too, because the channel 0 counter configuration is used by all the synchronous channels.
If a channel x is defined as a synchronous channel, it uses the following configuration fields of the channel 0 instead of its
own:
own:
CPRE0 field in PWM_CMR0 register instead of CPREx field in PWM_CMRx register (same source clock)
CPRD0 field in PWM_CMR0 register instead of CPRDx field in PWM_CMRx register (same period)
CALG0 field in PWM_CMR0 register instead of CALGx field in PWM_CMRx register (same alignment)
Thus writing these fields of a synchronous channel has no effect on the output waveform of this channel (except channel
0 of course).
0 of course).
Because counters of synchronous channels must start at the same time, they are all enabled together by enabling the
channel 0 (by the CHID0 bit in PWM_ENA register). In the same way, they are all disabled together by disabling channel
0 (by the CHID0 bit in PWM_DIS register). However, a synchronous channel x different from channel 0 can be enabled or
disabled independently from others (by the CHIDx bit in PWM_ENA and PWM_DIS registers).
channel 0 (by the CHID0 bit in PWM_ENA register). In the same way, they are all disabled together by disabling channel
0 (by the CHID0 bit in PWM_DIS register). However, a synchronous channel x different from channel 0 can be enabled or
disabled independently from others (by the CHIDx bit in PWM_ENA and PWM_DIS registers).
Defining a channel as a synchronous channel while it is an asynchronous channel (by writing the bit SYNCx to 1 while it
was at 0) is allowed only if the channel is disabled at this time (CHIDx = 0 in
was at 0) is allowed only if the channel is disabled at this time (CHIDx = 0 in
PWM_SR register)
. In the same way, defining
a channel as an asynchronous channel while it is a synchronous channel (by writing the SYNCx bit to 0 while it was 1) is
allowed only if the channel is disabled at this time.
allowed only if the channel is disabled at this time.
The field UPDM (Update Mode) in the PWM_SCM register allow to select one of the three methods to update the
registers of the synchronous channels:
registers of the synchronous channels:
Method 1 (UPDM = 0): the period value, the duty-cycle values and the dead-time values must be written by the
CPU in their respective update registers (respectively PWM_CPRDUPDx, PWM_CDTYUPDx and
PWM_DTUPDx).The update is triggered at the next PWM period as soon as the bit UPDULOCK in the
CPU in their respective update registers (respectively PWM_CPRDUPDx, PWM_CDTYUPDx and
PWM_DTUPDx).The update is triggered at the next PWM period as soon as the bit UPDULOCK in the
(PWM_SCUC) is set to 1 (see
).
Method 2 (UPDM = 1): the period value, the duty-cycle values, the dead-time values and the update period value
must be written by the CPU in their respective update registers (respectively PWM_CPRDUPDx,
PWM_CDTYUPDx and PWM_DTUPD). The update of the period value and of the dead-time values is triggered at
the next PWM period as soon as the bit UPDULOCK in the
must be written by the CPU in their respective update registers (respectively PWM_CPRDUPDx,
PWM_CDTYUPDx and PWM_DTUPD). The update of the period value and of the dead-time values is triggered at
the next PWM period as soon as the bit UPDULOCK in the