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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

By using registers PWM_OSS and PWM_OSC, the output selection of PWM outputs is done asynchronously to the
channel counter, as soon as the register is written.

The value of the current output selection can be read in PWM_OS.

While overriding PWM outputs, the channel counters continue to run, only the PWM outputs are forced to user defined
values.

6 inputs provide fault protection which can force any of the PWM output pair to a programmable value. This mechanism
has priority over output overriding.

The polarity level of the fault inputs is configured by the FPOL field in the 

fault inputs coming from internal peripherals such as ADC, Timer Counter, to name but a few, the polarity level must be
FPOL = 1. For fault inputs coming from external GPIO pins the polarity level depends on the user's implementation. 

The configuration of the Fault Activation Mode (FMOD bit in PWMC_FMR) depends on the peripheral generating the
fault. If the corresponding peripheral does not have “Fault Clear” management, then the FMOD configuration to use must
be FMOD = 1, to avoid spurious fault detection. Check the corresponding peripheral documentation for details on
handling fault generation.

The fault inputs can be glitch filtered or not in function of the FFIL field in the PWM_FMR register. When the filter is
activated, glitches on fault inputs with a width inferior to the PWM master clock (MCK) period are rejected.

A fault becomes active as soon as its corresponding fault input has a transition to the programmed polarity level. If the
corresponding bit FMOD is set to 0 in the PWM_FMR register, the fault remains active as long as the fault input is at this
polarity level. If the corresponding FMOD bit is set to 1, the fault remains active until the fault input is not at this polarity
level anymore and until it is cleared by writing the corresponding bit FCLR in the 

 (PWM_FSR), the user can read the current level of the fault

inputs by means of the field FIV, and can know which fault is currently active thanks to the FS field.

Each fault can be taken into account or not by the fault protection mechanism in each channel. To be taken into account
in the channel x, the fault y must be enabled by the bit FPEx[y] in the “PWM Fault Protection Enable Registers”
(PWM_FPE1). However the synchronous channels (see 

fault enable bits, but those of the channel 0 (bits FPE0[y]).

The fault protection on a channel is triggered when this channel is enabled and when any one of the faults that are
enabled for this channel is active. It can be triggered even if the PWM master clock (MCK) is not running but only by a
fault input that is not glitch filtered.

FIV0

fault input 0

Fault protection

on PWM

channel x

Glitch
Filter

FFIL0

from fault 0

from fault y

1

0

=

FPOL0

FMOD0

1

0

Fault 0 Status
FS0

FIV1

Glitch
Filter

FFIL1

1

0

=

FPOL1

SET

CLR

FMOD1

1

0

OUT

Fault 1 Status
FS1

fault input 1

from fault 1

1

0

0

1

From Output

Override

OOHx

OOLx

From Output

Override

FPVHx

FPVLx

PWMHx

PWMLx

fault input y

FMOD1

SET

CLR

Write FCLR0 at 1

OUT

FMOD0

Write FCLR1 at 1

SYNCx

1

0

FPEx[0]

FPE0[0]

SYNCx

1

0

FPEx[1]

FPE0[1]